URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr] - Blame information for rev 5

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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
 
 
 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Available hyper_sources - for debug and ip models
        None Found
 
@N: MT206 |Auto Constrain mode is enabled
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Pass             CPU time               Worst Slack             Luts / Registers
------------------------------------------------------------
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
 
@S |Clock Optimization Summary
 
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
 
 
 
============================== Non-Gated/Non-Generated Clocks ===============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------------
@K:CKID0001       clk                 port                   8          DDwD_Top.ascii_reg[6]
=============================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
 
 
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jan 13 00:54:42 2017
#
 
 
Top view:               DisplayDriverWrapper
Requested Frequency:    1220.4 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
Performance Summary
*******************
 
 
Worst slack in design: -0.145
 
                             Requested      Estimated      Requested     Estimated                Clock        Clock
Starting Clock               Frequency      Frequency      Period        Period        Slack      Type         Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk     1220.4 MHz     1037.3 MHz     0.819         0.964         -0.145     inferred     Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
 
 
Clock Relationships
*******************
 
Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
-------------------------------------------------------------------------------------------------------------------------------------------
Starting                  Ending                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  0.819       -0.145  |  No paths    -      |  No paths    -      |  No paths    -
===========================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
Interface Information
*********************
 
No IO constraint found
 
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|clk
====================================
 
 
 
Starting Points with Worst Slack
********************************
 
                          Starting                                                          Arrival
Instance                  Reference                    Type        Pin     Net              Time        Slack
                          Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[0]     0.753       -0.145
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[1]     0.753       -0.145
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[2]     0.753       -0.145
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[3]     0.753       -0.145
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[4]     0.753       -0.145
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[5]     0.753       -0.145
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[6]     0.753       -0.145
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[7]     0.753       -0.145
==============================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
                          Starting                                                          Required
Instance                  Reference                    Type        Pin     Net              Time         Slack
                          Clock
---------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[0]     0.608        -0.145
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[1]     0.608        -0.145
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[2]     0.608        -0.145
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[3]     0.608        -0.145
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[4]     0.608        -0.145
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[5]     0.608        -0.145
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[6]     0.608        -0.145
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[7]     0.608        -0.145
===============================================================================================================
 
 
 
Worst Path Information
***********************
 
 
Path information for path number 1:
      Requested Period:                      0.819
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.608
 
    - Propagation time:                      0.753
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.145
 
    Number of logic level(s):                0
    Starting point:                          DDwD_Top.ascii_reg[0] / Q
    Ending point:                            DDwD_Top.ascii_reg[0] / D
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net                        Pin      Pin               Arrival     No. of
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0]     FD1S3IX     Q        Out     0.753     0.753       -
ascii_reg[0]              Net         -        -       -         -           1
DDwD_Top.ascii_reg[0]     FD1S3IX     D        In      0.000     0.753       -
=======================================================================================
 
 
Path information for path number 2:
      Requested Period:                      0.819
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.608
 
    - Propagation time:                      0.753
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.145
 
    Number of logic level(s):                0
    Starting point:                          DDwD_Top.ascii_reg[1] / Q
    Ending point:                            DDwD_Top.ascii_reg[1] / D
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net                        Pin      Pin               Arrival     No. of
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[1]     FD1S3JX     Q        Out     0.753     0.753       -
ascii_reg[1]              Net         -        -       -         -           1
DDwD_Top.ascii_reg[1]     FD1S3JX     D        In      0.000     0.753       -
=======================================================================================
 
 
Path information for path number 3:
      Requested Period:                      0.819
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.608
 
    - Propagation time:                      0.753
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.145
 
    Number of logic level(s):                0
    Starting point:                          DDwD_Top.ascii_reg[2] / Q
    Ending point:                            DDwD_Top.ascii_reg[2] / D
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net                        Pin      Pin               Arrival     No. of
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[2]     FD1S3IX     Q        Out     0.753     0.753       -
ascii_reg[2]              Net         -        -       -         -           1
DDwD_Top.ascii_reg[2]     FD1S3IX     D        In      0.000     0.753       -
=======================================================================================
 
 
Path information for path number 4:
      Requested Period:                      0.819
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.608
 
    - Propagation time:                      0.753
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.145
 
    Number of logic level(s):                0
    Starting point:                          DDwD_Top.ascii_reg[3] / Q
    Ending point:                            DDwD_Top.ascii_reg[3] / D
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net                        Pin      Pin               Arrival     No. of
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[3]     FD1S3IX     Q        Out     0.753     0.753       -
ascii_reg[3]              Net         -        -       -         -           1
DDwD_Top.ascii_reg[3]     FD1S3IX     D        In      0.000     0.753       -
=======================================================================================
 
 
Path information for path number 5:
      Requested Period:                      0.819
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.608
 
    - Propagation time:                      0.753
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.145
 
    Number of logic level(s):                0
    Starting point:                          DDwD_Top.ascii_reg[4] / Q
    Ending point:                            DDwD_Top.ascii_reg[4] / D
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net                        Pin      Pin               Arrival     No. of
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[4]     FD1S3JX     Q        Out     0.753     0.753       -
ascii_reg[4]              Net         -        -       -         -           1
DDwD_Top.ascii_reg[4]     FD1S3JX     D        In      0.000     0.753       -
=======================================================================================
 
 
 
##### END OF TIMING REPORT #####]
 
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 8 of 43848 (0%)
PIC Latch:       0
I/O cells:       18
 
 
Details:
FD1S3IX:        5
FD1S3JX:        3
GSR:            1
IB:             2
OB:             16
PUR:            1
VHI:            2
VLO:            1
false:          1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Fri Jan 13 00:54:42 2017
 
###########################################################]

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	liubenoff	`Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31`
2			`Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.`
3			`Product Version L-2016.03L-1`
4
5			`Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)`
6
7			`@N: MF248 \|Running in 64-bit mode.`
8			`@N: MF666 \|Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)`
9
10			`Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)`
11
12
13			`Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)`
14
15
16			`Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)`
17
18
19			`Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)`
20
21
22
23			`Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
24
25
26			`Available hyper_sources - for debug and ip models`
27			`None Found`
28
29			`@N: MT206 \|Auto Constrain mode is enabled`
30
31			`Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
32
33
34			`Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
35
36
37			`Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
38
39
40			`Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
41
42
43			`Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
44
45
46			`Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
47
48
49			`Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
50
51
52			`Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
53
54
55			`Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
56
57
58			`Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
59
60			`Pass CPU time Worst Slack Luts / Registers`
61			`------------------------------------------------------------`
62
63			`Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
64
65			`@N: FX164 \|The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.`
66
67			`Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
68
69
70
71			`@S \|Clock Optimization Summary`
72
73
74			`#### START OF CLOCK OPTIMIZATION REPORT #####[`
75
76			`1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)`
77
78
79
80			`============================== Non-Gated/Non-Generated Clocks ===============================`
81			`Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance`
82			`---------------------------------------------------------------------------------------------`
83			`@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]`
84			`=============================================================================================`
85
86
87			`##### END OF CLOCK OPTIMIZATION REPORT ######]`
88
89
90			`Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)`
91
92			`Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm`
93
94			`Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)`
95
96			`Writing EDIF Netlist and constraint files`
97			`@N: FX1056 \|Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi`
98			`L-2016.03L-1`
99			`@N: BW106 \|Synplicity Constraint File capacitance units using default value of 1pF`
100
101			`Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)`
102
103
104			`Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)`
105
106			`@W: MT420 \|Found inferred clock DisplayDriverWrapper\|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"`
107
108
109			`##### START OF TIMING REPORT #####[`
110			`# Timing Report written on Fri Jan 13 00:54:42 2017`
111			`#`
112
113
114			`Top view: DisplayDriverWrapper`
115			`Requested Frequency: 1220.4 MHz`
116			`Wire load mode: top`
117			`Paths requested: 5`
118			`Constraint File(s):`
119			`@N: MT320 \|Timing report estimates place and route data. Please look at the place and route timing report for final timing.`
120
121			`@N: MT322 \|Clock constraints cover only FF-to-FF paths associated with the clock.`
122
123
124
125			`Performance Summary`
126			`*******************`
127
128
129			`Worst slack in design: -0.145`
130
131			`Requested Estimated Requested Estimated Clock Clock`
132			`Starting Clock Frequency Frequency Period Period Slack Type Group`
133			`------------------------------------------------------------------------------------------------------------------------------------`
134			`DisplayDriverWrapper\|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0`
135			`====================================================================================================================================`
136
137
138
139
140
141			`Clock Relationships`
142			`*******************`
143
144			`Clocks \| rise to rise \| fall to fall \| rise to fall \| fall to rise`
145			`-------------------------------------------------------------------------------------------------------------------------------------------`
146			`Starting Ending \| constraint slack \| constraint slack \| constraint slack \| constraint slack`
147			`-------------------------------------------------------------------------------------------------------------------------------------------`
148			`DisplayDriverWrapper\|clk DisplayDriverWrapper\|clk \| 0.819 -0.145 \| No paths - \| No paths - \| No paths -`
149			`===========================================================================================================================================`
150			`Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.`
151			`'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.`
152
153
154
155			`Interface Information`
156			`*********************`
157
158			`No IO constraint found`
159
160
161
162			`====================================`
163			`Detailed Report for Clock: DisplayDriverWrapper\|clk`
164			`====================================`
165
166
167
168			`Starting Points with Worst Slack`
169			`********************************`
170
171			`Starting Arrival`
172			`Instance Reference Type Pin Net Time Slack`
173			`Clock`
174			`--------------------------------------------------------------------------------------------------------------`
175			`DDwD_Top.ascii_reg[0] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145`
176			`DDwD_Top.ascii_reg[1] DisplayDriverWrapper\|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145`
177			`DDwD_Top.ascii_reg[2] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145`
178			`DDwD_Top.ascii_reg[3] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145`
179			`DDwD_Top.ascii_reg[4] DisplayDriverWrapper\|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145`
180			`DDwD_Top.ascii_reg[5] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145`
181			`DDwD_Top.ascii_reg[6] DisplayDriverWrapper\|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145`
182			`DDwD_Top.ascii_reg[7] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145`
183			`==============================================================================================================`
184
185
186			`Ending Points with Worst Slack`
187			`******************************`
188
189			`Starting Required`
190			`Instance Reference Type Pin Net Time Slack`
191			`Clock`
192			`---------------------------------------------------------------------------------------------------------------`
193			`DDwD_Top.ascii_reg[0] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[0] 0.608 -0.145`
194			`DDwD_Top.ascii_reg[1] DisplayDriverWrapper\|clk FD1S3JX D ascii_reg[1] 0.608 -0.145`
195			`DDwD_Top.ascii_reg[2] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[2] 0.608 -0.145`
196			`DDwD_Top.ascii_reg[3] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[3] 0.608 -0.145`
197			`DDwD_Top.ascii_reg[4] DisplayDriverWrapper\|clk FD1S3JX D ascii_reg[4] 0.608 -0.145`
198			`DDwD_Top.ascii_reg[5] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[5] 0.608 -0.145`
199			`DDwD_Top.ascii_reg[6] DisplayDriverWrapper\|clk FD1S3JX D ascii_reg[6] 0.608 -0.145`
200			`DDwD_Top.ascii_reg[7] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[7] 0.608 -0.145`
201			`===============================================================================================================`
202
203
204
205			`Worst Path Information`
206			`***********************`
207
208
209			`Path information for path number 1:`
210			`Requested Period: 0.819`
211			`- Setup time: 0.211`
212			`+ Clock delay at ending point: 0.000 (ideal)`
213			`= Required time: 0.608`
214
215			`- Propagation time: 0.753`
216			`- Clock delay at starting point: 0.000 (ideal)`
217			`= Slack (critical) : -0.145`
218
219			`Number of logic level(s): 0`
220			`Starting point: DDwD_Top.ascii_reg[0] / Q`
221			`Ending point: DDwD_Top.ascii_reg[0] / D`
222			`The start point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
223			`The end point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
224
225			`Instance / Net Pin Pin Arrival No. of`
226			`Name Type Name Dir Delay Time Fan Out(s)`
227			`---------------------------------------------------------------------------------------`
228			`DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -`
229			`ascii_reg[0] Net - - - - 1`
230			`DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -`
231			`=======================================================================================`
232
233
234			`Path information for path number 2:`
235			`Requested Period: 0.819`
236			`- Setup time: 0.211`
237			`+ Clock delay at ending point: 0.000 (ideal)`
238			`= Required time: 0.608`
239
240			`- Propagation time: 0.753`
241			`- Clock delay at starting point: 0.000 (ideal)`
242			`= Slack (critical) : -0.145`
243
244			`Number of logic level(s): 0`
245			`Starting point: DDwD_Top.ascii_reg[1] / Q`
246			`Ending point: DDwD_Top.ascii_reg[1] / D`
247			`The start point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
248			`The end point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
249
250			`Instance / Net Pin Pin Arrival No. of`
251			`Name Type Name Dir Delay Time Fan Out(s)`
252			`---------------------------------------------------------------------------------------`
253			`DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -`
254			`ascii_reg[1] Net - - - - 1`
255			`DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -`
256			`=======================================================================================`
257
258
259			`Path information for path number 3:`
260			`Requested Period: 0.819`
261			`- Setup time: 0.211`
262			`+ Clock delay at ending point: 0.000 (ideal)`
263			`= Required time: 0.608`
264
265			`- Propagation time: 0.753`
266			`- Clock delay at starting point: 0.000 (ideal)`
267			`= Slack (critical) : -0.145`
268
269			`Number of logic level(s): 0`
270			`Starting point: DDwD_Top.ascii_reg[2] / Q`
271			`Ending point: DDwD_Top.ascii_reg[2] / D`
272			`The start point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
273			`The end point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
274
275			`Instance / Net Pin Pin Arrival No. of`
276			`Name Type Name Dir Delay Time Fan Out(s)`
277			`---------------------------------------------------------------------------------------`
278			`DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -`
279			`ascii_reg[2] Net - - - - 1`
280			`DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -`
281			`=======================================================================================`
282
283
284			`Path information for path number 4:`
285			`Requested Period: 0.819`
286			`- Setup time: 0.211`
287			`+ Clock delay at ending point: 0.000 (ideal)`
288			`= Required time: 0.608`
289
290			`- Propagation time: 0.753`
291			`- Clock delay at starting point: 0.000 (ideal)`
292			`= Slack (critical) : -0.145`
293
294			`Number of logic level(s): 0`
295			`Starting point: DDwD_Top.ascii_reg[3] / Q`
296			`Ending point: DDwD_Top.ascii_reg[3] / D`
297			`The start point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
298			`The end point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
299
300			`Instance / Net Pin Pin Arrival No. of`
301			`Name Type Name Dir Delay Time Fan Out(s)`
302			`---------------------------------------------------------------------------------------`
303			`DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -`
304			`ascii_reg[3] Net - - - - 1`
305			`DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -`
306			`=======================================================================================`
307
308
309			`Path information for path number 5:`
310			`Requested Period: 0.819`
311			`- Setup time: 0.211`
312			`+ Clock delay at ending point: 0.000 (ideal)`
313			`= Required time: 0.608`
314
315			`- Propagation time: 0.753`
316			`- Clock delay at starting point: 0.000 (ideal)`
317			`= Slack (critical) : -0.145`
318
319			`Number of logic level(s): 0`
320			`Starting point: DDwD_Top.ascii_reg[4] / Q`
321			`Ending point: DDwD_Top.ascii_reg[4] / D`
322			`The start point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
323			`The end point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
324
325			`Instance / Net Pin Pin Arrival No. of`
326			`Name Type Name Dir Delay Time Fan Out(s)`
327			`---------------------------------------------------------------------------------------`
328			`DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -`
329			`ascii_reg[4] Net - - - - 1`
330			`DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -`
331			`=======================================================================================`
332
333
334
335			`##### END OF TIMING REPORT #####]`
336
337			`Constraints that could not be applied`
338			`None`
339
340			`Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)`
341
342
343			`Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)`
344
345			`---------------------------------------`
346			`Resource Usage Report`
347			`Part: lfe5um5g_45f-8`
348
349			`Register bits: 8 of 43848 (0%)`
350			`PIC Latch: 0`
351			`I/O cells: 18`
352
353
354			`Details:`
355			`FD1S3IX: 5`
356			`FD1S3JX: 3`
357			`GSR: 1`
358			`IB: 2`
359			`OB: 16`
360			`PUR: 1`
361			`VHI: 2`
362			`VLO: 1`
363			`false: 1`
364			`Mapper successful!`
365
366			`At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)`
367
368			`Process took 0h:00m:02s realtime, 0h:00m:01s cputime`
369			`# Fri Jan 13 00:54:42 2017`
370
371			`###########################################################]`