URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr] - Blame information for rev 6

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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
 
 
 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Available hyper_sources - for debug and ip models
        None Found
 
@N: MT206 |Auto Constrain mode is enabled
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Pass             CPU time               Worst Slack             Luts / Registers
------------------------------------------------------------
   1            0h:00m:00s                  -0.70ns                1 /         8
   2            0h:00m:00s                  -0.70ns                1 /         8
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 0 LUTs via timing driven replication
 
   3            0h:00m:00s                  -0.64ns                1 /         9
 
   4            0h:00m:00s                  -0.64ns                1 /         9
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
 
@S |Clock Optimization Summary
 
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
 
 
 
============================= Non-Gated/Non-Generated Clocks ==============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
-------------------------------------------------------------------------------------------
@K:CKID0001       button              port                   9          symbol_scan_cntr[0]
===========================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
 
 
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Tue Jan 17 01:19:13 2017
#
 
 
Top view:               DisplayDriverWrapper
Requested Frequency:    443.5 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
Performance Summary
*******************
 
 
Worst slack in design: -0.398
 
                                Requested     Estimated     Requested     Estimated                Clock        Clock
Starting Clock                  Frequency     Frequency     Period        Period        Slack      Type         Group
-------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button     443.5 MHz     377.0 MHz     2.255         2.652         -0.398     inferred     Autoconstr_clkgroup_0
=====================================================================================================================================
 
 
 
 
 
Clock Relationships
*******************
 
Clocks                                                    |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
-------------------------------------------------------------------------------------------------------------------------------------------------
Starting                     Ending                       |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-------------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|button  DisplayDriverWrapper|button  |  2.255       -0.398  |  No paths    -      |  No paths    -      |  No paths    -
=================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
Interface Information
*********************
 
No IO constraint found
 
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|button
====================================
 
 
 
Starting Points with Worst Slack
********************************
 
                             Starting                                                                         Arrival
Instance                     Reference                       Type        Pin     Net                          Time        Slack
                             Clock
--------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[1]          DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr[1]          0.933       -0.398
symbol_scan_cntr[2]          DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr[2]          0.933       -0.398
symbol_scan_cntr[3]          DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr[3]          0.933       -0.339
symbol_scan_cntr[4]          DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr[4]          0.933       -0.339
symbol_scan_cntr[5]          DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr[5]          0.933       -0.280
symbol_scan_cntr[6]          DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr[6]          0.933       -0.280
symbol_scan_cntr_fast[0]     DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr_fast[0]     0.753       -0.277
symbol_scan_cntr[7]          DisplayDriverWrapper|button     FD1S3DX     Q       symbol_scan_cntr[7]          0.798       0.570
================================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
                             Starting                                                                      Required
Instance                     Reference                       Type        Pin     Net                       Time         Slack
                             Clock
------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[7]     2.044        -0.398
symbol_scan_cntr[5]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[5]     2.044        -0.339
symbol_scan_cntr[6]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[6]     2.044        -0.339
symbol_scan_cntr[3]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[3]     2.044        -0.280
symbol_scan_cntr[4]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[4]     2.044        -0.280
symbol_scan_cntr[1]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[1]     2.044        -0.100
symbol_scan_cntr[2]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[2]     2.044        -0.100
symbol_scan_cntr[0]          DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[0]     2.044        0.570
symbol_scan_cntr_fast[0]     DisplayDriverWrapper|button     FD1S3DX     D       symbol_scan_cntr_s[0]     2.044        0.570
==============================================================================================================================
 
 
 
Worst Path Information
***********************
 
 
Path information for path number 1:
      Requested Period:                      2.255
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.044
 
    - Propagation time:                      2.442
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.398
 
    Number of logic level(s):                4
    Starting point:                          symbol_scan_cntr[1] / Q
    Ending point:                            symbol_scan_cntr[7] / D
    The start point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1]           FD1S3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[1]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[1]     CCU2C       A0       In      0.000     0.933       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.835       -
symbol_scan_cntr_cry[6]       Net         -        -       -         -           1
symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.835       -
symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.442       -
symbol_scan_cntr_s[7]         Net         -        -       -         -           1
symbol_scan_cntr[7]           FD1S3DX     D        In      0.000     2.442       -
===========================================================================================
 
 
Path information for path number 2:
      Requested Period:                      2.255
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.044
 
    - Propagation time:                      2.442
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.398
 
    Number of logic level(s):                4
    Starting point:                          symbol_scan_cntr[2] / Q
    Ending point:                            symbol_scan_cntr[7] / D
    The start point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2]           FD1S3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[2]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[1]     CCU2C       A1       In      0.000     0.933       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.835       -
symbol_scan_cntr_cry[6]       Net         -        -       -         -           1
symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.835       -
symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.442       -
symbol_scan_cntr_s[7]         Net         -        -       -         -           1
symbol_scan_cntr[7]           FD1S3DX     D        In      0.000     2.442       -
===========================================================================================
 
 
Path information for path number 3:
      Requested Period:                      2.255
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.044
 
    - Propagation time:                      2.382
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.339
 
    Number of logic level(s):                3
    Starting point:                          symbol_scan_cntr[3] / Q
    Ending point:                            symbol_scan_cntr[7] / D
    The start point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[3]           FD1S3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[3]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[3]     CCU2C       A0       In      0.000     0.933       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[6]       Net         -        -       -         -           1
symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.382       -
symbol_scan_cntr_s[7]         Net         -        -       -         -           1
symbol_scan_cntr[7]           FD1S3DX     D        In      0.000     2.382       -
===========================================================================================
 
 
Path information for path number 4:
      Requested Period:                      2.255
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.044
 
    - Propagation time:                      2.382
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.339
 
    Number of logic level(s):                3
    Starting point:                          symbol_scan_cntr[4] / Q
    Ending point:                            symbol_scan_cntr[7] / D
    The start point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[4]           FD1S3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[4]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[3]     CCU2C       A1       In      0.000     0.933       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[6]       Net         -        -       -         -           1
symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.382       -
symbol_scan_cntr_s[7]         Net         -        -       -         -           1
symbol_scan_cntr[7]           FD1S3DX     D        In      0.000     2.382       -
===========================================================================================
 
 
Path information for path number 5:
      Requested Period:                      2.255
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.044
 
    - Propagation time:                      2.382
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.339
 
    Number of logic level(s):                3
    Starting point:                          symbol_scan_cntr[1] / Q
    Ending point:                            symbol_scan_cntr[5] / D
    The start point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|button [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1]           FD1S3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[1]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[1]     CCU2C       A0       In      0.000     0.933       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[5]     CCU2C       S0       Out     0.607     2.382       -
symbol_scan_cntr_s[5]         Net         -        -       -         -           1
symbol_scan_cntr[5]           FD1S3DX     D        In      0.000     2.382       -
===========================================================================================
 
 
 
##### END OF TIMING REPORT #####]
 
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 9 of 43848 (0%)
PIC Latch:       0
I/O cells:       18
 
 
Details:
CCU2C:          5
FD1S3DX:        9
GSR:            1
IB:             2
INV:            1
OB:             16
PUR:            1
ROM128X1A:      14
VHI:            1
VLO:            1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Jan 17 01:19:13 2017
 
###########################################################]

Line No.	Rev	Author	Line
1	5	liubenoff	`Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31`
2			`Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.`
3			`Product Version L-2016.03L-1`
4
5			`Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)`
6
7			`@N: MF248 \|Running in 64-bit mode.`
8			`@N: MF666 \|Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)`
9
10			`Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)`
11
12
13			`Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)`
14
15
16			`Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)`
17
18
19			`Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)`
20
21
22
23			`Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
24
25
26			`Available hyper_sources - for debug and ip models`
27			`None Found`
28
29			`@N: MT206 \|Auto Constrain mode is enabled`
30
31			`Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
32
33	6	liubenoff	`@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5\|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]`
34	5	liubenoff
35			`Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
36
37
38			`Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
39
40
41			`Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
42
43
44			`Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
45
46
47			`Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
48
49
50			`Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
51
52
53			`Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
54
55
56			`Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
57
58
59			`Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
60
61			`Pass CPU time Worst Slack Luts / Registers`
62			`------------------------------------------------------------`
63	6	liubenoff	`1 0h:00m:00s -0.70ns 1 / 8`
64			`2 0h:00m:00s -0.70ns 1 / 8`
65			`@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5\|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.`
66			`Timing driven replication report`
67			`Added 1 Registers via timing driven replication`
68			`Added 0 LUTs via timing driven replication`
69	5	liubenoff
70	6	liubenoff	`3 0h:00m:00s -0.64ns 1 / 9`
71
72			`4 0h:00m:00s -0.64ns 1 / 9`
73
74	5	liubenoff	`Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
75
76			`@N: FX164 \|The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.`
77
78	6	liubenoff	`Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)`
79	5	liubenoff
80
81
82			`@S \|Clock Optimization Summary`
83
84
85			`#### START OF CLOCK OPTIMIZATION REPORT #####[`
86
87	6	liubenoff	`1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)`
88	5	liubenoff
89
90
91	6	liubenoff	`============================= Non-Gated/Non-Generated Clocks ==============================`
92			`Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance`
93			`-------------------------------------------------------------------------------------------`
94			`@K:CKID0001 button port 9 symbol_scan_cntr[0]`
95			`===========================================================================================`
96	5	liubenoff
97
98			`##### END OF CLOCK OPTIMIZATION REPORT ######]`
99
100
101			`Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)`
102
103			`Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm`
104
105	6	liubenoff	`Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
106	5	liubenoff
107			`Writing EDIF Netlist and constraint files`
108			`@N: FX1056 \|Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi`
109			`L-2016.03L-1`
110			`@N: BW106 \|Synplicity Constraint File capacitance units using default value of 1pF`
111
112	6	liubenoff	`Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)`
113	5	liubenoff
114
115	6	liubenoff	`Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)`
116	5	liubenoff
117	6	liubenoff	`@W: MT420 \|Found inferred clock DisplayDriverWrapper\|button with period 2.25ns. Please declare a user-defined clock on object "p:button"`
118	5	liubenoff
119
120			`##### START OF TIMING REPORT #####[`
121	6	liubenoff	`# Timing Report written on Tue Jan 17 01:19:13 2017`
122	5	liubenoff	`#`
123
124
125			`Top view: DisplayDriverWrapper`
126	6	liubenoff	`Requested Frequency: 443.5 MHz`
127	5	liubenoff	`Wire load mode: top`
128			`Paths requested: 5`
129			`Constraint File(s):`
130			`@N: MT320 \|Timing report estimates place and route data. Please look at the place and route timing report for final timing.`
131
132			`@N: MT322 \|Clock constraints cover only FF-to-FF paths associated with the clock.`
133
134
135
136			`Performance Summary`
137			`*******************`
138
139
140	6	liubenoff	`Worst slack in design: -0.398`
141	5	liubenoff
142	6	liubenoff	`Requested Estimated Requested Estimated Clock Clock`
143			`Starting Clock Frequency Frequency Period Period Slack Type Group`
144			`-------------------------------------------------------------------------------------------------------------------------------------`
145			`DisplayDriverWrapper\|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0`
146			`=====================================================================================================================================`
147	5	liubenoff
148
149
150
151
152			`Clock Relationships`
153			`*******************`
154
155	6	liubenoff	`Clocks \| rise to rise \| fall to fall \| rise to fall \| fall to rise`
156			`-------------------------------------------------------------------------------------------------------------------------------------------------`
157			`Starting Ending \| constraint slack \| constraint slack \| constraint slack \| constraint slack`
158			`-------------------------------------------------------------------------------------------------------------------------------------------------`
159			`DisplayDriverWrapper\|button DisplayDriverWrapper\|button \| 2.255 -0.398 \| No paths - \| No paths - \| No paths -`
160			`=================================================================================================================================================`
161	5	liubenoff	`Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.`
162			`'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.`
163
164
165
166			`Interface Information`
167			`*********************`
168
169			`No IO constraint found`
170
171
172
173			`====================================`
174	6	liubenoff	`Detailed Report for Clock: DisplayDriverWrapper\|button`
175	5	liubenoff	`====================================`
176
177
178
179			`Starting Points with Worst Slack`
180			`********************************`
181
182	6	liubenoff	`Starting Arrival`
183			`Instance Reference Type Pin Net Time Slack`
184			`Clock`
185			`--------------------------------------------------------------------------------------------------------------------------------`
186			`symbol_scan_cntr[1] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398`
187			`symbol_scan_cntr[2] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398`
188			`symbol_scan_cntr[3] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339`
189			`symbol_scan_cntr[4] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339`
190			`symbol_scan_cntr[5] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280`
191			`symbol_scan_cntr[6] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280`
192			`symbol_scan_cntr_fast[0] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277`
193			`symbol_scan_cntr[7] DisplayDriverWrapper\|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570`
194			`================================================================================================================================`
195	5	liubenoff
196
197			`Ending Points with Worst Slack`
198			`******************************`
199
200	6	liubenoff	`Starting Required`
201			`Instance Reference Type Pin Net Time Slack`
202			`Clock`
203			`------------------------------------------------------------------------------------------------------------------------------`
204			`symbol_scan_cntr[7] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398`
205			`symbol_scan_cntr[5] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339`
206			`symbol_scan_cntr[6] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339`
207			`symbol_scan_cntr[3] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280`
208			`symbol_scan_cntr[4] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280`
209			`symbol_scan_cntr[1] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100`
210			`symbol_scan_cntr[2] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100`
211			`symbol_scan_cntr[0] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570`
212			`symbol_scan_cntr_fast[0] DisplayDriverWrapper\|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570`
213			`==============================================================================================================================`
214	5	liubenoff
215
216
217			`Worst Path Information`
218			`***********************`
219
220
221			`Path information for path number 1:`
222	6	liubenoff	`Requested Period: 2.255`
223	5	liubenoff	`- Setup time: 0.211`
224			`+ Clock delay at ending point: 0.000 (ideal)`
225	6	liubenoff	`= Required time: 2.044`
226	5	liubenoff
227	6	liubenoff	`- Propagation time: 2.442`
228	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
229	6	liubenoff	`= Slack (critical) : -0.398`
230	5	liubenoff
231	6	liubenoff	`Number of logic level(s): 4`
232			`Starting point: symbol_scan_cntr[1] / Q`
233			`Ending point: symbol_scan_cntr[7] / D`
234			`The start point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
235			`The end point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
236	5	liubenoff
237	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
238			`Name Type Name Dir Delay Time Fan Out(s)`
239			`-------------------------------------------------------------------------------------------`
240			`symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -`
241			`symbol_scan_cntr[1] Net - - - - 15`
242			`symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -`
243			`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -`
244			`symbol_scan_cntr_cry[2] Net - - - - 1`
245			`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -`
246			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -`
247			`symbol_scan_cntr_cry[4] Net - - - - 1`
248			`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -`
249			`symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -`
250			`symbol_scan_cntr_cry[6] Net - - - - 1`
251			`symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -`
252			`symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -`
253			`symbol_scan_cntr_s[7] Net - - - - 1`
254			`symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -`
255			`===========================================================================================`
256	5	liubenoff
257
258			`Path information for path number 2:`
259	6	liubenoff	`Requested Period: 2.255`
260	5	liubenoff	`- Setup time: 0.211`
261			`+ Clock delay at ending point: 0.000 (ideal)`
262	6	liubenoff	`= Required time: 2.044`
263	5	liubenoff
264	6	liubenoff	`- Propagation time: 2.442`
265	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
266	6	liubenoff	`= Slack (critical) : -0.398`
267	5	liubenoff
268	6	liubenoff	`Number of logic level(s): 4`
269			`Starting point: symbol_scan_cntr[2] / Q`
270			`Ending point: symbol_scan_cntr[7] / D`
271			`The start point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
272			`The end point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
273	5	liubenoff
274	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
275			`Name Type Name Dir Delay Time Fan Out(s)`
276			`-------------------------------------------------------------------------------------------`
277			`symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -`
278			`symbol_scan_cntr[2] Net - - - - 15`
279			`symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -`
280			`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -`
281			`symbol_scan_cntr_cry[2] Net - - - - 1`
282			`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -`
283			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -`
284			`symbol_scan_cntr_cry[4] Net - - - - 1`
285			`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -`
286			`symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -`
287			`symbol_scan_cntr_cry[6] Net - - - - 1`
288			`symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -`
289			`symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -`
290			`symbol_scan_cntr_s[7] Net - - - - 1`
291			`symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -`
292			`===========================================================================================`
293	5	liubenoff
294
295			`Path information for path number 3:`
296	6	liubenoff	`Requested Period: 2.255`
297	5	liubenoff	`- Setup time: 0.211`
298			`+ Clock delay at ending point: 0.000 (ideal)`
299	6	liubenoff	`= Required time: 2.044`
300	5	liubenoff
301	6	liubenoff	`- Propagation time: 2.382`
302	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
303	6	liubenoff	`= Slack (non-critical) : -0.339`
304	5	liubenoff
305	6	liubenoff	`Number of logic level(s): 3`
306			`Starting point: symbol_scan_cntr[3] / Q`
307			`Ending point: symbol_scan_cntr[7] / D`
308			`The start point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
309			`The end point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
310	5	liubenoff
311	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
312			`Name Type Name Dir Delay Time Fan Out(s)`
313			`-------------------------------------------------------------------------------------------`
314			`symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -`
315			`symbol_scan_cntr[3] Net - - - - 15`
316			`symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -`
317			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -`
318			`symbol_scan_cntr_cry[4] Net - - - - 1`
319			`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -`
320			`symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -`
321			`symbol_scan_cntr_cry[6] Net - - - - 1`
322			`symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -`
323			`symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -`
324			`symbol_scan_cntr_s[7] Net - - - - 1`
325			`symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -`
326			`===========================================================================================`
327	5	liubenoff
328
329			`Path information for path number 4:`
330	6	liubenoff	`Requested Period: 2.255`
331	5	liubenoff	`- Setup time: 0.211`
332			`+ Clock delay at ending point: 0.000 (ideal)`
333	6	liubenoff	`= Required time: 2.044`
334	5	liubenoff
335	6	liubenoff	`- Propagation time: 2.382`
336	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
337	6	liubenoff	`= Slack (non-critical) : -0.339`
338	5	liubenoff
339	6	liubenoff	`Number of logic level(s): 3`
340			`Starting point: symbol_scan_cntr[4] / Q`
341			`Ending point: symbol_scan_cntr[7] / D`
342			`The start point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
343			`The end point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
344	5	liubenoff
345	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
346			`Name Type Name Dir Delay Time Fan Out(s)`
347			`-------------------------------------------------------------------------------------------`
348			`symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -`
349			`symbol_scan_cntr[4] Net - - - - 15`
350			`symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -`
351			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -`
352			`symbol_scan_cntr_cry[4] Net - - - - 1`
353			`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -`
354			`symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -`
355			`symbol_scan_cntr_cry[6] Net - - - - 1`
356			`symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -`
357			`symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -`
358			`symbol_scan_cntr_s[7] Net - - - - 1`
359			`symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -`
360			`===========================================================================================`
361	5	liubenoff
362
363			`Path information for path number 5:`
364	6	liubenoff	`Requested Period: 2.255`
365	5	liubenoff	`- Setup time: 0.211`
366			`+ Clock delay at ending point: 0.000 (ideal)`
367	6	liubenoff	`= Required time: 2.044`
368	5	liubenoff
369	6	liubenoff	`- Propagation time: 2.382`
370	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
371	6	liubenoff	`= Slack (non-critical) : -0.339`
372	5	liubenoff
373	6	liubenoff	`Number of logic level(s): 3`
374			`Starting point: symbol_scan_cntr[1] / Q`
375			`Ending point: symbol_scan_cntr[5] / D`
376			`The start point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
377			`The end point is clocked by DisplayDriverWrapper\|button [rising] on pin CK`
378	5	liubenoff
379	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
380			`Name Type Name Dir Delay Time Fan Out(s)`
381			`-------------------------------------------------------------------------------------------`
382			`symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -`
383			`symbol_scan_cntr[1] Net - - - - 15`
384			`symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -`
385			`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -`
386			`symbol_scan_cntr_cry[2] Net - - - - 1`
387			`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -`
388			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -`
389			`symbol_scan_cntr_cry[4] Net - - - - 1`
390			`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -`
391			`symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -`
392			`symbol_scan_cntr_s[5] Net - - - - 1`
393			`symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -`
394			`===========================================================================================`
395	5	liubenoff
396
397
398			`##### END OF TIMING REPORT #####]`
399
400			`Constraints that could not be applied`
401			`None`
402
403	6	liubenoff	`Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)`
404	5	liubenoff
405
406	6	liubenoff	`Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)`
407	5	liubenoff
408			`---------------------------------------`
409			`Resource Usage Report`
410			`Part: lfe5um5g_45f-8`
411
412	6	liubenoff	`Register bits: 9 of 43848 (0%)`
413	5	liubenoff	`PIC Latch: 0`
414			`I/O cells: 18`
415
416
417			`Details:`
418	6	liubenoff	`CCU2C: 5`
419			`FD1S3DX: 9`
420	5	liubenoff	`GSR: 1`
421			`IB: 2`
422	6	liubenoff	`INV: 1`
423	5	liubenoff	`OB: 16`
424			`PUR: 1`
425	6	liubenoff	`ROM128X1A: 14`
426			`VHI: 1`
427	5	liubenoff	`VLO: 1`
428			`Mapper successful!`
429
430	6	liubenoff	`At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)`
431	5	liubenoff
432	6	liubenoff	`Process took 0h:00m:01s realtime, 0h:00m:01s cputime`
433			`# Tue Jan 17 01:19:13 2017`
434	5	liubenoff
435			`###########################################################]`

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr] - Blame information for rev 6