URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr] - Blame information for rev 9

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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.03L-1
 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
 
@N: MF248 |Running in 64-bit mode.
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
 
 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
 
 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
 
 
 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Available hyper_sources - for debug and ip models
        None Found
 
@N: MT206 |Auto Constrain mode is enabled
 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":74:8:74:9|Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]
 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
Pass             CPU time               Worst Slack             Luts / Registers
------------------------------------------------------------
   1            0h:00m:00s                  -0.76ns                6 /        13
   2            0h:00m:00s                  -0.76ns                6 /        13
 
   3            0h:00m:00s                  -0.62ns                7 /        13
 
 
   4            0h:00m:00s                  -0.58ns                6 /        13
 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
 
@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
 
 
@S |Clock Optimization Summary
 
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
 
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001       clk                 port                   13         bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
 
 
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
 
Writing EDIF Netlist and constraint files
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
L-2016.03L-1
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
 
@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view:               display_driver_wrapper
Requested Frequency:    433.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
Performance Summary
*******************
 
 
Worst slack in design: -0.407
 
                               Requested     Estimated     Requested     Estimated                Clock        Clock
Starting Clock                 Frequency     Frequency     Period        Period        Slack      Type         Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk     433.9 MHz     368.8 MHz     2.305         2.712         -0.407     inferred     Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
 
 
Clock Relationships
*******************
 
Clocks                                                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting                    Ending                      |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk  display_driver_wrapper|clk  |  2.305       -0.407  |  No paths    -      |  No paths    -      |  No paths    -
===============================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
Interface Information
*********************
 
No IO constraint found
 
 
 
====================================
Detailed Report for Clock: display_driver_wrapper|clk
====================================
 
 
 
Starting Points with Worst Slack
********************************
 
                        Starting                                                                   Arrival
Instance                Reference                      Type        Pin     Net                     Time        Slack
                        Clock
---------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[0]     display_driver_wrapper|clk     FD1P3DX     Q       symbol_scan_cntr[0]     0.933       -0.407
symbol_scan_cntr[1]     display_driver_wrapper|clk     FD1P3DX     Q       symbol_scan_cntr[1]     0.933       -0.348
symbol_scan_cntr[2]     display_driver_wrapper|clk     FD1P3DX     Q       symbol_scan_cntr[2]     0.933       -0.348
symbol_scan_cntr[3]     display_driver_wrapper|clk     FD1P3DX     Q       symbol_scan_cntr[3]     0.933       -0.289
symbol_scan_cntr[4]     display_driver_wrapper|clk     FD1P3DX     Q       symbol_scan_cntr[4]     0.933       -0.289
symbol_scan_cntr[5]     display_driver_wrapper|clk     FD1P3DX     Q       symbol_scan_cntr[5]     0.933       -0.230
symbol_scan_cntr[6]     display_driver_wrapper|clk     FD1P3DX     Q       symbol_scan_cntr[6]     0.933       -0.230
bttn_state_fifo[3]      display_driver_wrapper|clk     FD1S3JX     Q       bttn_state_fifo[3]      0.798       0.123
bttn_state              display_driver_wrapper|clk     FD1S3AX     Q       bttn_state_i            0.753       0.168
bttn_state_fifo[1]      display_driver_wrapper|clk     FD1S3JX     Q       bttn_state_fifo[1]      0.838       0.606
=====================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
                        Starting                                                                               Required
Instance                Reference                      Type        Pin     Net                                 Time         Slack
                        Clock
----------------------------------------------------------------------------------------------------------------------------------
symbol_scan_cntr[7]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[7]               2.094        -0.407
symbol_scan_cntr[5]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[5]               2.094        -0.348
symbol_scan_cntr[6]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[6]               2.094        -0.348
symbol_scan_cntr[3]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[3]               2.094        -0.289
symbol_scan_cntr[4]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[4]               2.094        -0.289
symbol_scan_cntr[1]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[1]               2.094        -0.230
symbol_scan_cntr[2]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[2]               2.094        -0.230
symbol_scan_cntr[0]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     2.122        0.123
symbol_scan_cntr[1]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     2.122        0.123
symbol_scan_cntr[2]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     2.122        0.123
==================================================================================================================================
 
 
 
Worst Path Information
***********************
 
 
Path information for path number 1:
      Requested Period:                      2.305
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.094
 
    - Propagation time:                      2.501
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.407
 
    Number of logic level(s):                5
    Starting point:                          symbol_scan_cntr[0] / Q
    Ending point:                            symbol_scan_cntr[7] / D
    The start point is clocked by            display_driver_wrapper|clk [rising] on pin CK
    The end   point is clocked by            display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0]           FD1P3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[0]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[0]     CCU2C       A1       In      0.000     0.933       -
symbol_scan_cntr_cry_0[0]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[0]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[1]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.835       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.835       -
symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.894       -
symbol_scan_cntr_cry[6]       Net         -        -       -         -           1
symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.894       -
symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.501       -
symbol_scan_cntr_s[7]         Net         -        -       -         -           1
symbol_scan_cntr[7]           FD1P3DX     D        In      0.000     2.501       -
===========================================================================================
 
 
Path information for path number 2:
      Requested Period:                      2.305
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.094
 
    - Propagation time:                      2.442
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.348
 
    Number of logic level(s):                4
    Starting point:                          symbol_scan_cntr[1] / Q
    Ending point:                            symbol_scan_cntr[7] / D
    The start point is clocked by            display_driver_wrapper|clk [rising] on pin CK
    The end   point is clocked by            display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[1]           FD1P3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[1]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[1]     CCU2C       A0       In      0.000     0.933       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.835       -
symbol_scan_cntr_cry[6]       Net         -        -       -         -           1
symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.835       -
symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.442       -
symbol_scan_cntr_s[7]         Net         -        -       -         -           1
symbol_scan_cntr[7]           FD1P3DX     D        In      0.000     2.442       -
===========================================================================================
 
 
Path information for path number 3:
      Requested Period:                      2.305
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.094
 
    - Propagation time:                      2.442
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.348
 
    Number of logic level(s):                4
    Starting point:                          symbol_scan_cntr[2] / Q
    Ending point:                            symbol_scan_cntr[7] / D
    The start point is clocked by            display_driver_wrapper|clk [rising] on pin CK
    The end   point is clocked by            display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[2]           FD1P3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[2]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[1]     CCU2C       A1       In      0.000     0.933       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[5]     CCU2C       COUT     Out     0.059     1.835       -
symbol_scan_cntr_cry[6]       Net         -        -       -         -           1
symbol_scan_cntr_s_0[7]       CCU2C       CIN      In      0.000     1.835       -
symbol_scan_cntr_s_0[7]       CCU2C       S0       Out     0.607     2.442       -
symbol_scan_cntr_s[7]         Net         -        -       -         -           1
symbol_scan_cntr[7]           FD1P3DX     D        In      0.000     2.442       -
===========================================================================================
 
 
Path information for path number 4:
      Requested Period:                      2.305
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.094
 
    - Propagation time:                      2.442
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.348
 
    Number of logic level(s):                4
    Starting point:                          symbol_scan_cntr[0] / Q
    Ending point:                            symbol_scan_cntr[5] / D
    The start point is clocked by            display_driver_wrapper|clk [rising] on pin CK
    The end   point is clocked by            display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0]           FD1P3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[0]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[0]     CCU2C       A1       In      0.000     0.933       -
symbol_scan_cntr_cry_0[0]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[0]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[1]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.835       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.835       -
symbol_scan_cntr_cry_0[5]     CCU2C       S0       Out     0.607     2.442       -
symbol_scan_cntr_s[5]         Net         -        -       -         -           1
symbol_scan_cntr[5]           FD1P3DX     D        In      0.000     2.442       -
===========================================================================================
 
 
Path information for path number 5:
      Requested Period:                      2.305
    - Setup time:                            0.211
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.094
 
    - Propagation time:                      2.442
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.348
 
    Number of logic level(s):                4
    Starting point:                          symbol_scan_cntr[0] / Q
    Ending point:                            symbol_scan_cntr[6] / D
    The start point is clocked by            display_driver_wrapper|clk [rising] on pin CK
    The end   point is clocked by            display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net                            Pin      Pin               Arrival     No. of
Name                          Type        Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
symbol_scan_cntr[0]           FD1P3DX     Q        Out     0.933     0.933       -
symbol_scan_cntr[0]           Net         -        -       -         -           15
symbol_scan_cntr_cry_0[0]     CCU2C       A1       In      0.000     0.933       -
symbol_scan_cntr_cry_0[0]     CCU2C       COUT     Out     0.784     1.717       -
symbol_scan_cntr_cry[0]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[1]     CCU2C       CIN      In      0.000     1.717       -
symbol_scan_cntr_cry_0[1]     CCU2C       COUT     Out     0.059     1.776       -
symbol_scan_cntr_cry[2]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[3]     CCU2C       CIN      In      0.000     1.776       -
symbol_scan_cntr_cry_0[3]     CCU2C       COUT     Out     0.059     1.835       -
symbol_scan_cntr_cry[4]       Net         -        -       -         -           1
symbol_scan_cntr_cry_0[5]     CCU2C       CIN      In      0.000     1.835       -
symbol_scan_cntr_cry_0[5]     CCU2C       S1       Out     0.607     2.442       -
symbol_scan_cntr_s[6]         Net         -        -       -         -           1
symbol_scan_cntr[6]           FD1P3DX     D        In      0.000     2.442       -
===========================================================================================
 
 
 
##### END OF TIMING REPORT #####]
 
Constraints that could not be applied
None
 
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
 
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
 
---------------------------------------
Resource Usage Report
Part: lfe5um5g_45f-8
 
Register bits: 13 of 43848 (0%)
PIC Latch:       0
I/O cells:       18
 
 
Details:
CCU2C:          5
FD1P3DX:        8
FD1S3AX:        1
FD1S3JX:        3
GSR:            1
IB:             3
IFS1P3JX:       1
INV:            2
OB:             15
ORCALUT4:       4
PUR:            1
ROM128X1A:      14
VHI:            1
VLO:            1
Mapper successful!
 
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jan 18 01:08:17 2017
 
###########################################################]

Line No.	Rev	Author	Line
1	5	liubenoff	`Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31`
2			`Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.`
3			`Product Version L-2016.03L-1`
4
5			`Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)`
6
7			`@N: MF248 \|Running in 64-bit mode.`
8			`@N: MF666 \|Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)`
9
10			`Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)`
11
12
13			`Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)`
14
15
16			`Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)`
17
18
19			`Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)`
20
21
22
23			`Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
24
25
26			`Available hyper_sources - for debug and ip models`
27			`None Found`
28
29			`@N: MT206 \|Auto Constrain mode is enabled`
30
31			`Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
32
33	9	liubenoff	`@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":74:8:74:9\|Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]`
34	5	liubenoff
35			`Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
36
37
38			`Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
39
40
41			`Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
42
43
44			`Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
45
46
47			`Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
48
49
50	9	liubenoff	`Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)`
51	5	liubenoff
52
53			`Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
54
55
56			`Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
57
58
59			`Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
60
61			`Pass CPU time Worst Slack Luts / Registers`
62			`------------------------------------------------------------`
63	9	liubenoff	`1 0h:00m:00s -0.76ns 6 / 13`
64			`2 0h:00m:00s -0.76ns 6 / 13`
65	5	liubenoff
66	9	liubenoff	`3 0h:00m:00s -0.62ns 7 / 13`
67	6	liubenoff
68
69	9	liubenoff	`4 0h:00m:00s -0.58ns 6 / 13`
70
71	5	liubenoff	`Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)`
72
73			`@N: FX164 \|The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.`
74
75	6	liubenoff	`Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)`
76	5	liubenoff
77	9	liubenoff	`@N: MT611 :\|Automatically generated clock display_driver_wrapper\|bttn_state_derived_clock is not used and is being removed`
78	5	liubenoff
79
80			`@S \|Clock Optimization Summary`
81
82
83			`#### START OF CLOCK OPTIMIZATION REPORT #####[`
84
85	9	liubenoff	`1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)`
86	5	liubenoff
87	9	liubenoff	`8 instances converted, 0 sequential instances remain driven by gated/generated clocks`
88	5	liubenoff
89	9	liubenoff	`=========================== Non-Gated/Non-Generated Clocks ============================`
90			`Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance`
91			`---------------------------------------------------------------------------------------`
92			`@K:CKID0001 clk port 13 bttn_state`
93			`=======================================================================================`
94	5	liubenoff
95
96			`##### END OF CLOCK OPTIMIZATION REPORT ######]`
97
98
99			`Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)`
100
101			`Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm`
102
103	9	liubenoff	`Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)`
104	5	liubenoff
105			`Writing EDIF Netlist and constraint files`
106			`@N: FX1056 \|Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi`
107			`L-2016.03L-1`
108			`@N: BW106 \|Synplicity Constraint File capacitance units using default value of 1pF`
109
110	9	liubenoff	`Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)`
111	5	liubenoff
112
113	6	liubenoff	`Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)`
114	5	liubenoff
115	9	liubenoff	`@W: MT420 \|Found inferred clock display_driver_wrapper\|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"`
116	5	liubenoff
117
118			`##### START OF TIMING REPORT #####[`
119	9	liubenoff	`# Timing Report written on Wed Jan 18 01:08:17 2017`
120	5	liubenoff	`#`
121
122
123	9	liubenoff	`Top view: display_driver_wrapper`
124			`Requested Frequency: 433.9 MHz`
125	5	liubenoff	`Wire load mode: top`
126			`Paths requested: 5`
127			`Constraint File(s):`
128			`@N: MT320 \|Timing report estimates place and route data. Please look at the place and route timing report for final timing.`
129
130			`@N: MT322 \|Clock constraints cover only FF-to-FF paths associated with the clock.`
131
132
133
134			`Performance Summary`
135			`*******************`
136
137
138	9	liubenoff	`Worst slack in design: -0.407`
139	5	liubenoff
140	9	liubenoff	`Requested Estimated Requested Estimated Clock Clock`
141			`Starting Clock Frequency Frequency Period Period Slack Type Group`
142			`------------------------------------------------------------------------------------------------------------------------------------`
143			`display_driver_wrapper\|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0`
144			`====================================================================================================================================`
145	5	liubenoff
146
147
148
149
150			`Clock Relationships`
151			`*******************`
152
153	9	liubenoff	`Clocks \| rise to rise \| fall to fall \| rise to fall \| fall to rise`
154			`-----------------------------------------------------------------------------------------------------------------------------------------------`
155			`Starting Ending \| constraint slack \| constraint slack \| constraint slack \| constraint slack`
156			`-----------------------------------------------------------------------------------------------------------------------------------------------`
157			`display_driver_wrapper\|clk display_driver_wrapper\|clk \| 2.305 -0.407 \| No paths - \| No paths - \| No paths -`
158			`===============================================================================================================================================`
159	5	liubenoff	`Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.`
160			`'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.`
161
162
163
164			`Interface Information`
165			`*********************`
166
167			`No IO constraint found`
168
169
170
171			`====================================`
172	9	liubenoff	`Detailed Report for Clock: display_driver_wrapper\|clk`
173	5	liubenoff	`====================================`
174
175
176
177			`Starting Points with Worst Slack`
178			`********************************`
179
180	9	liubenoff	`Starting Arrival`
181			`Instance Reference Type Pin Net Time Slack`
182			`Clock`
183			`---------------------------------------------------------------------------------------------------------------------`
184			`symbol_scan_cntr[0] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407`
185			`symbol_scan_cntr[1] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348`
186			`symbol_scan_cntr[2] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348`
187			`symbol_scan_cntr[3] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289`
188			`symbol_scan_cntr[4] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289`
189			`symbol_scan_cntr[5] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230`
190			`symbol_scan_cntr[6] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230`
191			`bttn_state_fifo[3] display_driver_wrapper\|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123`
192			`bttn_state display_driver_wrapper\|clk FD1S3AX Q bttn_state_i 0.753 0.168`
193			`bttn_state_fifo[1] display_driver_wrapper\|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606`
194			`=====================================================================================================================`
195	5	liubenoff
196
197			`Ending Points with Worst Slack`
198			`******************************`
199
200	9	liubenoff	`Starting Required`
201			`Instance Reference Type Pin Net Time Slack`
202			`Clock`
203			`----------------------------------------------------------------------------------------------------------------------------------`
204			`symbol_scan_cntr[7] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407`
205			`symbol_scan_cntr[5] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348`
206			`symbol_scan_cntr[6] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348`
207			`symbol_scan_cntr[3] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289`
208			`symbol_scan_cntr[4] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289`
209			`symbol_scan_cntr[1] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230`
210			`symbol_scan_cntr[2] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230`
211			`symbol_scan_cntr[0] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123`
212			`symbol_scan_cntr[1] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123`
213			`symbol_scan_cntr[2] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123`
214			`==================================================================================================================================`
215	5	liubenoff
216
217
218			`Worst Path Information`
219			`***********************`
220
221
222			`Path information for path number 1:`
223	9	liubenoff	`Requested Period: 2.305`
224	5	liubenoff	`- Setup time: 0.211`
225			`+ Clock delay at ending point: 0.000 (ideal)`
226	9	liubenoff	`= Required time: 2.094`
227	5	liubenoff
228	9	liubenoff	`- Propagation time: 2.501`
229	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
230	9	liubenoff	`= Slack (critical) : -0.407`
231	5	liubenoff
232	9	liubenoff	`Number of logic level(s): 5`
233			`Starting point: symbol_scan_cntr[0] / Q`
234	6	liubenoff	`Ending point: symbol_scan_cntr[7] / D`
235	9	liubenoff	`The start point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
236			`The end point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
237	5	liubenoff
238	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
239			`Name Type Name Dir Delay Time Fan Out(s)`
240			`-------------------------------------------------------------------------------------------`
241	9	liubenoff	`symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -`
242			`symbol_scan_cntr[0] Net - - - - 15`
243			`symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -`
244			`symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -`
245			`symbol_scan_cntr_cry[0] Net - - - - 1`
246			`symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -`
247			`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -`
248	6	liubenoff	`symbol_scan_cntr_cry[2] Net - - - - 1`
249	9	liubenoff	`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -`
250			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -`
251	6	liubenoff	`symbol_scan_cntr_cry[4] Net - - - - 1`
252	9	liubenoff	`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -`
253			`symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -`
254	6	liubenoff	`symbol_scan_cntr_cry[6] Net - - - - 1`
255	9	liubenoff	`symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -`
256			`symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -`
257	6	liubenoff	`symbol_scan_cntr_s[7] Net - - - - 1`
258	9	liubenoff	`symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -`
259	6	liubenoff	`===========================================================================================`
260	5	liubenoff
261
262			`Path information for path number 2:`
263	9	liubenoff	`Requested Period: 2.305`
264	5	liubenoff	`- Setup time: 0.211`
265			`+ Clock delay at ending point: 0.000 (ideal)`
266	9	liubenoff	`= Required time: 2.094`
267	5	liubenoff
268	6	liubenoff	`- Propagation time: 2.442`
269	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
270	9	liubenoff	`= Slack (non-critical) : -0.348`
271	5	liubenoff
272	6	liubenoff	`Number of logic level(s): 4`
273	9	liubenoff	`Starting point: symbol_scan_cntr[1] / Q`
274	6	liubenoff	`Ending point: symbol_scan_cntr[7] / D`
275	9	liubenoff	`The start point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
276			`The end point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
277	5	liubenoff
278	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
279			`Name Type Name Dir Delay Time Fan Out(s)`
280			`-------------------------------------------------------------------------------------------`
281	9	liubenoff	`symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -`
282			`symbol_scan_cntr[1] Net - - - - 15`
283			`symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -`
284	6	liubenoff	`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -`
285			`symbol_scan_cntr_cry[2] Net - - - - 1`
286			`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -`
287			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -`
288			`symbol_scan_cntr_cry[4] Net - - - - 1`
289			`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -`
290			`symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -`
291			`symbol_scan_cntr_cry[6] Net - - - - 1`
292			`symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -`
293			`symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -`
294			`symbol_scan_cntr_s[7] Net - - - - 1`
295	9	liubenoff	`symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -`
296	6	liubenoff	`===========================================================================================`
297	5	liubenoff
298
299			`Path information for path number 3:`
300	9	liubenoff	`Requested Period: 2.305`
301	5	liubenoff	`- Setup time: 0.211`
302			`+ Clock delay at ending point: 0.000 (ideal)`
303	9	liubenoff	`= Required time: 2.094`
304	5	liubenoff
305	9	liubenoff	`- Propagation time: 2.442`
306	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
307	9	liubenoff	`= Slack (non-critical) : -0.348`
308	5	liubenoff
309	9	liubenoff	`Number of logic level(s): 4`
310			`Starting point: symbol_scan_cntr[2] / Q`
311	6	liubenoff	`Ending point: symbol_scan_cntr[7] / D`
312	9	liubenoff	`The start point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
313			`The end point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
314	5	liubenoff
315	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
316			`Name Type Name Dir Delay Time Fan Out(s)`
317			`-------------------------------------------------------------------------------------------`
318	9	liubenoff	`symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -`
319			`symbol_scan_cntr[2] Net - - - - 15`
320			`symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -`
321			`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -`
322			`symbol_scan_cntr_cry[2] Net - - - - 1`
323			`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -`
324			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -`
325	6	liubenoff	`symbol_scan_cntr_cry[4] Net - - - - 1`
326	9	liubenoff	`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -`
327			`symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -`
328	6	liubenoff	`symbol_scan_cntr_cry[6] Net - - - - 1`
329	9	liubenoff	`symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -`
330			`symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -`
331	6	liubenoff	`symbol_scan_cntr_s[7] Net - - - - 1`
332	9	liubenoff	`symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -`
333	6	liubenoff	`===========================================================================================`
334	5	liubenoff
335
336			`Path information for path number 4:`
337	9	liubenoff	`Requested Period: 2.305`
338	5	liubenoff	`- Setup time: 0.211`
339			`+ Clock delay at ending point: 0.000 (ideal)`
340	9	liubenoff	`= Required time: 2.094`
341	5	liubenoff
342	9	liubenoff	`- Propagation time: 2.442`
343	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
344	9	liubenoff	`= Slack (non-critical) : -0.348`
345	5	liubenoff
346	9	liubenoff	`Number of logic level(s): 4`
347			`Starting point: symbol_scan_cntr[0] / Q`
348			`Ending point: symbol_scan_cntr[5] / D`
349			`The start point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
350			`The end point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
351	5	liubenoff
352	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
353			`Name Type Name Dir Delay Time Fan Out(s)`
354			`-------------------------------------------------------------------------------------------`
355	9	liubenoff	`symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -`
356			`symbol_scan_cntr[0] Net - - - - 15`
357			`symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -`
358			`symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -`
359			`symbol_scan_cntr_cry[0] Net - - - - 1`
360			`symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -`
361			`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -`
362			`symbol_scan_cntr_cry[2] Net - - - - 1`
363			`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -`
364			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -`
365	6	liubenoff	`symbol_scan_cntr_cry[4] Net - - - - 1`
366	9	liubenoff	`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -`
367			`symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -`
368			`symbol_scan_cntr_s[5] Net - - - - 1`
369			`symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -`
370	6	liubenoff	`===========================================================================================`
371	5	liubenoff
372
373			`Path information for path number 5:`
374	9	liubenoff	`Requested Period: 2.305`
375	5	liubenoff	`- Setup time: 0.211`
376			`+ Clock delay at ending point: 0.000 (ideal)`
377	9	liubenoff	`= Required time: 2.094`
378	5	liubenoff
379	9	liubenoff	`- Propagation time: 2.442`
380	5	liubenoff	`- Clock delay at starting point: 0.000 (ideal)`
381	9	liubenoff	`= Slack (non-critical) : -0.348`
382	5	liubenoff
383	9	liubenoff	`Number of logic level(s): 4`
384			`Starting point: symbol_scan_cntr[0] / Q`
385			`Ending point: symbol_scan_cntr[6] / D`
386			`The start point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
387			`The end point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
388	5	liubenoff
389	6	liubenoff	`Instance / Net Pin Pin Arrival No. of`
390			`Name Type Name Dir Delay Time Fan Out(s)`
391			`-------------------------------------------------------------------------------------------`
392	9	liubenoff	`symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -`
393			`symbol_scan_cntr[0] Net - - - - 15`
394			`symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -`
395			`symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -`
396			`symbol_scan_cntr_cry[0] Net - - - - 1`
397			`symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -`
398			`symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -`
399	6	liubenoff	`symbol_scan_cntr_cry[2] Net - - - - 1`
400	9	liubenoff	`symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -`
401			`symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -`
402	6	liubenoff	`symbol_scan_cntr_cry[4] Net - - - - 1`
403	9	liubenoff	`symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -`
404			`symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -`
405			`symbol_scan_cntr_s[6] Net - - - - 1`
406			`symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -`
407	6	liubenoff	`===========================================================================================`
408	5	liubenoff
409
410
411			`##### END OF TIMING REPORT #####]`
412
413			`Constraints that could not be applied`
414			`None`
415
416	6	liubenoff	`Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)`
417	5	liubenoff
418
419	6	liubenoff	`Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)`
420	5	liubenoff
421			`---------------------------------------`
422			`Resource Usage Report`
423			`Part: lfe5um5g_45f-8`
424
425	9	liubenoff	`Register bits: 13 of 43848 (0%)`
426	5	liubenoff	`PIC Latch: 0`
427			`I/O cells: 18`
428
429
430			`Details:`
431	6	liubenoff	`CCU2C: 5`
432	9	liubenoff	`FD1P3DX: 8`
433			`FD1S3AX: 1`
434			`FD1S3JX: 3`
435	5	liubenoff	`GSR: 1`
436	9	liubenoff	`IB: 3`
437			`IFS1P3JX: 1`
438			`INV: 2`
439			`OB: 15`
440			`ORCALUT4: 4`
441	5	liubenoff	`PUR: 1`
442	6	liubenoff	`ROM128X1A: 14`
443			`VHI: 1`
444	5	liubenoff	`VLO: 1`
445			`Mapper successful!`
446
447	6	liubenoff	`At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)`
448	5	liubenoff
449	6	liubenoff	`Process took 0h:00m:01s realtime, 0h:00m:01s cputime`
450	9	liubenoff	`# Wed Jan 18 01:08:17 2017`
451	5	liubenoff
452			`###########################################################]`

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr] - Blame information for rev 9