URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr_Min] - Blame information for rev 9

Details | Compare with Previous | View Log


 
 
##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jan 18 01:08:17 2017
#
 
 
Top view:               display_driver_wrapper
Requested Frequency:    433.9 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
Performance Summary
*******************
 
 
Worst slack in design: 0.439
 
                               Requested     Estimated     Requested     Estimated                Clock        Clock
Starting Clock                 Frequency     Frequency     Period        Period        Slack      Type         Group
------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk     433.9 MHz     368.8 MHz     2.305         2.712         -0.407     inferred     Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
Clock Relationships
*******************
 
Clocks                                                  |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
----------------------------------------------------------------------------------------------------------------------------------------------
Starting                    Ending                      |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------
display_driver_wrapper|clk  display_driver_wrapper|clk  |  0.000       0.439  |  No paths    -      |  No paths    -      |  No paths    -
==============================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
Interface Information
*********************
 
No IO constraint found
 
 
 
====================================
Detailed Report for Clock: display_driver_wrapper|clk
====================================
 
 
 
Starting Points with Worst Slack
********************************
 
                           Starting                                                                    Arrival
Instance                   Reference                      Type         Pin     Net                     Time        Slack
                           Clock
------------------------------------------------------------------------------------------------------------------------
bttn_state_fifo[1]         display_driver_wrapper|clk     FD1S3JX      Q       bttn_state_fifo[1]      0.587       0.439
bttn_state_fifo[2]         display_driver_wrapper|clk     FD1S3JX      Q       bttn_state_fifo[2]      0.587       0.439
bttn_state_fifo_0io[0]     display_driver_wrapper|clk     IFS1P3JX     Q       bttn_state_fifo[0]      0.587       0.439
symbol_scan_cntr[7]        display_driver_wrapper|clk     FD1P3DX      Q       symbol_scan_cntr[7]     0.559       0.884
symbol_scan_cntr[0]        display_driver_wrapper|clk     FD1P3DX      Q       symbol_scan_cntr[0]     0.653       0.979
symbol_scan_cntr[1]        display_driver_wrapper|clk     FD1P3DX      Q       symbol_scan_cntr[1]     0.653       0.979
symbol_scan_cntr[2]        display_driver_wrapper|clk     FD1P3DX      Q       symbol_scan_cntr[2]     0.653       0.979
symbol_scan_cntr[3]        display_driver_wrapper|clk     FD1P3DX      Q       symbol_scan_cntr[3]     0.653       0.979
symbol_scan_cntr[4]        display_driver_wrapper|clk     FD1P3DX      Q       symbol_scan_cntr[4]     0.653       0.979
symbol_scan_cntr[5]        display_driver_wrapper|clk     FD1P3DX      Q       symbol_scan_cntr[5]     0.653       0.979
========================================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
                        Starting                                                                               Required
Instance                Reference                      Type        Pin     Net                                 Time         Slack
                        Clock
---------------------------------------------------------------------------------------------------------------------------------
bttn_state_fifo[1]      display_driver_wrapper|clk     FD1S3JX     D       bttn_state_fifo[0]                  0.148        0.439
bttn_state_fifo[2]      display_driver_wrapper|clk     FD1S3JX     D       bttn_state_fifo[1]                  0.148        0.439
bttn_state_fifo[3]      display_driver_wrapper|clk     FD1S3JX     D       bttn_state_fifo[2]                  0.148        0.439
bttn_state              display_driver_wrapper|clk     FD1S3AX     D       bttn_stateand                       0.148        0.679
symbol_scan_cntr[7]     display_driver_wrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[7]               0.148        0.884
symbol_scan_cntr[0]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933
symbol_scan_cntr[1]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933
symbol_scan_cntr[2]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933
symbol_scan_cntr[3]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933
symbol_scan_cntr[4]     display_driver_wrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933
=================================================================================================================================
 
 
 
Worst Path Information
***********************
 
 
Path information for path number 1:
    Propagation time:                        0.587
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.148
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     0.439
 
    Number of logic level(s):                0
    Starting point:                          bttn_state_fifo[1] / Q
    Ending point:                            bttn_state_fifo[2] / D
    The start point is clocked by            display_driver_wrapper|clk [rising] on pin CK
    The end   point is clocked by            display_driver_wrapper|clk [rising] on pin CK
 
Instance / Net                     Pin      Pin               Arrival     No. of
Name                   Type        Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------
bttn_state_fifo[1]     FD1S3JX     Q        Out     0.587     0.587       -
bttn_state_fifo[1]     Net         -        -       -         -           3
bttn_state_fifo[2]     FD1S3JX     D        In      0.000     0.587       -
====================================================================================
 
 
 
##### END OF TIMING REPORT #####]
 
Constraints that could not be applied
None

Line No.	Rev	Author	Line
1	5	liubenoff
2
3			`##### START OF TIMING REPORT #####[`
4	9	liubenoff	`# Timing Report written on Wed Jan 18 01:08:17 2017`
5	5	liubenoff	`#`
6
7
8	9	liubenoff	`Top view: display_driver_wrapper`
9			`Requested Frequency: 433.9 MHz`
10	5	liubenoff	`Wire load mode: top`
11			`Paths requested: 5`
12			`Constraint File(s):`
13			`@N: MT320 \|Timing report estimates place and route data. Please look at the place and route timing report for final timing.`
14
15			`@N: MT322 \|Clock constraints cover only FF-to-FF paths associated with the clock.`
16
17
18
19			`Performance Summary`
20			`*******************`
21
22
23	9	liubenoff	`Worst slack in design: 0.439`
24	5	liubenoff
25	9	liubenoff	`Requested Estimated Requested Estimated Clock Clock`
26			`Starting Clock Frequency Frequency Period Period Slack Type Group`
27			`------------------------------------------------------------------------------------------------------------------------------------`
28			`display_driver_wrapper\|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0`
29			`====================================================================================================================================`
30	5	liubenoff
31
32
33			`Clock Relationships`
34			`*******************`
35
36	9	liubenoff	`Clocks \| rise to rise \| fall to fall \| rise to fall \| fall to rise`
37			`----------------------------------------------------------------------------------------------------------------------------------------------`
38			`Starting Ending \| constraint slack \| constraint slack \| constraint slack \| constraint slack`
39			`----------------------------------------------------------------------------------------------------------------------------------------------`
40			`display_driver_wrapper\|clk display_driver_wrapper\|clk \| 0.000 0.439 \| No paths - \| No paths - \| No paths -`
41			`==============================================================================================================================================`
42	5	liubenoff	`Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.`
43			`'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.`
44
45
46
47			`Interface Information`
48			`*********************`
49
50			`No IO constraint found`
51
52
53
54			`====================================`
55	9	liubenoff	`Detailed Report for Clock: display_driver_wrapper\|clk`
56	5	liubenoff	`====================================`
57
58
59
60			`Starting Points with Worst Slack`
61			`********************************`
62
63	9	liubenoff	`Starting Arrival`
64			`Instance Reference Type Pin Net Time Slack`
65			`Clock`
66			`------------------------------------------------------------------------------------------------------------------------`
67			`bttn_state_fifo[1] display_driver_wrapper\|clk FD1S3JX Q bttn_state_fifo[1] 0.587 0.439`
68			`bttn_state_fifo[2] display_driver_wrapper\|clk FD1S3JX Q bttn_state_fifo[2] 0.587 0.439`
69			`bttn_state_fifo_0io[0] display_driver_wrapper\|clk IFS1P3JX Q bttn_state_fifo[0] 0.587 0.439`
70			`symbol_scan_cntr[7] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[7] 0.559 0.884`
71			`symbol_scan_cntr[0] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[0] 0.653 0.979`
72			`symbol_scan_cntr[1] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[1] 0.653 0.979`
73			`symbol_scan_cntr[2] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[2] 0.653 0.979`
74			`symbol_scan_cntr[3] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[3] 0.653 0.979`
75			`symbol_scan_cntr[4] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[4] 0.653 0.979`
76			`symbol_scan_cntr[5] display_driver_wrapper\|clk FD1P3DX Q symbol_scan_cntr[5] 0.653 0.979`
77			`========================================================================================================================`
78	5	liubenoff
79
80			`Ending Points with Worst Slack`
81			`******************************`
82
83	9	liubenoff	`Starting Required`
84			`Instance Reference Type Pin Net Time Slack`
85			`Clock`
86			`---------------------------------------------------------------------------------------------------------------------------------`
87			`bttn_state_fifo[1] display_driver_wrapper\|clk FD1S3JX D bttn_state_fifo[0] 0.148 0.439`
88			`bttn_state_fifo[2] display_driver_wrapper\|clk FD1S3JX D bttn_state_fifo[1] 0.148 0.439`
89			`bttn_state_fifo[3] display_driver_wrapper\|clk FD1S3JX D bttn_state_fifo[2] 0.148 0.439`
90			`bttn_state display_driver_wrapper\|clk FD1S3AX D bttn_stateand 0.148 0.679`
91			`symbol_scan_cntr[7] display_driver_wrapper\|clk FD1P3DX D symbol_scan_cntr_s[7] 0.148 0.884`
92			`symbol_scan_cntr[0] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933`
93			`symbol_scan_cntr[1] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933`
94			`symbol_scan_cntr[2] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933`
95			`symbol_scan_cntr[3] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933`
96			`symbol_scan_cntr[4] display_driver_wrapper\|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 0.128 0.933`
97			`=================================================================================================================================`
98	5	liubenoff
99
100
101			`Worst Path Information`
102			`***********************`
103
104
105			`Path information for path number 1:`
106	9	liubenoff	`Propagation time: 0.587`
107	5	liubenoff	`+ Clock delay at starting point: 0.000 (ideal)`
108			`- Requested Period: 0.000`
109			`- Hold time: 0.148`
110			`- Clock delay at ending point: 0.000 (ideal)`
111	9	liubenoff	`= Slack (critical) : 0.439`
112	5	liubenoff
113	9	liubenoff	`Number of logic level(s): 0`
114			`Starting point: bttn_state_fifo[1] / Q`
115			`Ending point: bttn_state_fifo[2] / D`
116			`The start point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
117			`The end point is clocked by display_driver_wrapper\|clk [rising] on pin CK`
118	5	liubenoff
119	9	liubenoff	`Instance / Net Pin Pin Arrival No. of`
120			`Name Type Name Dir Delay Time Fan Out(s)`
121			`------------------------------------------------------------------------------------`
122			`bttn_state_fifo[1] FD1S3JX Q Out 0.587 0.587 -`
123			`bttn_state_fifo[1] Net - - - - 3`
124			`bttn_state_fifo[2] FD1S3JX D In 0.000 0.587 -`
125			`====================================================================================`
126	5	liubenoff
127
128
129			`##### END OF TIMING REPORT #####]`
130
131			`Constraints that could not be applied`
132			`None`

Browse

Tools

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [DisplayDriverwDecoder_impl1_fpga_mapper.srr_Min] - Blame information for rev 9