URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [impl1_fpga_mapper.srr_Min] - Blame information for rev 5

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##### START OF TIMING REPORT #####[
# Timing Report written on Sun Jan 08 00:49:36 2017
#
 
 
Top view:               DisplayDriverWrapper
Requested Frequency:    1297.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
 
 
 
Performance Summary
*******************
 
 
Worst slack in design: 0.559
 
                             Requested      Estimated      Requested     Estimated                Clock        Clock
Starting Clock               Frequency      Frequency      Period        Period        Slack      Type         Group
------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk     1297.0 MHz     1102.5 MHz     0.771         0.907         -0.136     inferred     Autoconstr_clkgroup_0
====================================================================================================================================
 
 
 
Clock Relationships
*******************
 
Clocks                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
------------------------------------------------------------------------------------------------------------------------------------------
Starting                  Ending                    |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
------------------------------------------------------------------------------------------------------------------------------------------
DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  0.000       0.559  |  No paths    -      |  No paths    -      |  No paths    -
==========================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
 
 
 
Interface Information
*********************
 
No IO constraint found
 
 
 
====================================
Detailed Report for Clock: DisplayDriverWrapper|clk
====================================
 
 
 
Starting Points with Worst Slack
********************************
 
                          Starting                                                          Arrival
Instance                  Reference                    Type        Pin     Net              Time        Slack
                          Clock
-------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[0]     0.597       0.559
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[1]     0.597       0.559
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[2]     0.597       0.559
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[3]     0.597       0.559
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[4]     0.597       0.559
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[5]     0.597       0.559
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[6]     0.597       0.559
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[7]     0.597       0.559
=============================================================================================================
 
 
Ending Points with Worst Slack
******************************
 
                          Starting                                                          Required
Instance                  Reference                    Type        Pin     Net              Time         Slack
                          Clock
--------------------------------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[0]     0.038        0.559
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[1]     0.038        0.559
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[2]     0.038        0.559
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[3]     0.038        0.559
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[4]     0.038        0.559
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[5]     0.038        0.559
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[6]     0.038        0.559
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[7]     0.038        0.559
==============================================================================================================
 
 
 
Worst Path Information
***********************
 
 
Path information for path number 1:
    Propagation time:                        0.597
    + Clock delay at starting point:         0.000 (ideal)
    - Requested Period:                      0.000
    - Hold time:                             0.038
    - Clock delay at ending point:           0.000 (ideal)
    = Slack (critical) :                     0.559
 
    Number of logic level(s):                0
    Starting point:                          DDwD_Top.ascii_reg[0] / Q
    Ending point:                            DDwD_Top.ascii_reg[0] / D
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
 
Instance / Net                        Pin      Pin               Arrival     No. of
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------
DDwD_Top.ascii_reg[0]     FD1S3IX     Q        Out     0.597     0.597       -
ascii_reg[0]              Net         -        -       -         -           1
DDwD_Top.ascii_reg[0]     FD1S3IX     D        In      0.000     0.597       -
=======================================================================================
 
 
 
##### END OF TIMING REPORT #####]
 
Constraints that could not be applied
None

Line No.	Rev	Author	Line
1	5	liubenoff
2
3			`##### START OF TIMING REPORT #####[`
4			`# Timing Report written on Sun Jan 08 00:49:36 2017`
5			`#`
6
7
8			`Top view: DisplayDriverWrapper`
9			`Requested Frequency: 1297.0 MHz`
10			`Wire load mode: top`
11			`Paths requested: 5`
12			`Constraint File(s):`
13			`@N: MT320 \|Timing report estimates place and route data. Please look at the place and route timing report for final timing.`
14
15			`@N: MT322 \|Clock constraints cover only FF-to-FF paths associated with the clock.`
16
17
18
19			`Performance Summary`
20			`*******************`
21
22
23			`Worst slack in design: 0.559`
24
25			`Requested Estimated Requested Estimated Clock Clock`
26			`Starting Clock Frequency Frequency Period Period Slack Type Group`
27			`------------------------------------------------------------------------------------------------------------------------------------`
28			`DisplayDriverWrapper\|clk 1297.0 MHz 1102.5 MHz 0.771 0.907 -0.136 inferred Autoconstr_clkgroup_0`
29			`====================================================================================================================================`
30
31
32
33			`Clock Relationships`
34			`*******************`
35
36			`Clocks \| rise to rise \| fall to fall \| rise to fall \| fall to rise`
37			`------------------------------------------------------------------------------------------------------------------------------------------`
38			`Starting Ending \| constraint slack \| constraint slack \| constraint slack \| constraint slack`
39			`------------------------------------------------------------------------------------------------------------------------------------------`
40			`DisplayDriverWrapper\|clk DisplayDriverWrapper\|clk \| 0.000 0.559 \| No paths - \| No paths - \| No paths -`
41			`==========================================================================================================================================`
42			`Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.`
43			`'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.`
44
45
46
47			`Interface Information`
48			`*********************`
49
50			`No IO constraint found`
51
52
53
54			`====================================`
55			`Detailed Report for Clock: DisplayDriverWrapper\|clk`
56			`====================================`
57
58
59
60			`Starting Points with Worst Slack`
61			`********************************`
62
63			`Starting Arrival`
64			`Instance Reference Type Pin Net Time Slack`
65			`Clock`
66			`-------------------------------------------------------------------------------------------------------------`
67			`DDwD_Top.ascii_reg[0] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[0] 0.597 0.559`
68			`DDwD_Top.ascii_reg[1] DisplayDriverWrapper\|clk FD1S3JX Q ascii_reg[1] 0.597 0.559`
69			`DDwD_Top.ascii_reg[2] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[2] 0.597 0.559`
70			`DDwD_Top.ascii_reg[3] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[3] 0.597 0.559`
71			`DDwD_Top.ascii_reg[4] DisplayDriverWrapper\|clk FD1S3JX Q ascii_reg[4] 0.597 0.559`
72			`DDwD_Top.ascii_reg[5] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[5] 0.597 0.559`
73			`DDwD_Top.ascii_reg[6] DisplayDriverWrapper\|clk FD1S3JX Q ascii_reg[6] 0.597 0.559`
74			`DDwD_Top.ascii_reg[7] DisplayDriverWrapper\|clk FD1S3IX Q ascii_reg[7] 0.597 0.559`
75			`=============================================================================================================`
76
77
78			`Ending Points with Worst Slack`
79			`******************************`
80
81			`Starting Required`
82			`Instance Reference Type Pin Net Time Slack`
83			`Clock`
84			`--------------------------------------------------------------------------------------------------------------`
85			`DDwD_Top.ascii_reg[0] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[0] 0.038 0.559`
86			`DDwD_Top.ascii_reg[1] DisplayDriverWrapper\|clk FD1S3JX D ascii_reg[1] 0.038 0.559`
87			`DDwD_Top.ascii_reg[2] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[2] 0.038 0.559`
88			`DDwD_Top.ascii_reg[3] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[3] 0.038 0.559`
89			`DDwD_Top.ascii_reg[4] DisplayDriverWrapper\|clk FD1S3JX D ascii_reg[4] 0.038 0.559`
90			`DDwD_Top.ascii_reg[5] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[5] 0.038 0.559`
91			`DDwD_Top.ascii_reg[6] DisplayDriverWrapper\|clk FD1S3JX D ascii_reg[6] 0.038 0.559`
92			`DDwD_Top.ascii_reg[7] DisplayDriverWrapper\|clk FD1S3IX D ascii_reg[7] 0.038 0.559`
93			`==============================================================================================================`
94
95
96
97			`Worst Path Information`
98			`***********************`
99
100
101			`Path information for path number 1:`
102			`Propagation time: 0.597`
103			`+ Clock delay at starting point: 0.000 (ideal)`
104			`- Requested Period: 0.000`
105			`- Hold time: 0.038`
106			`- Clock delay at ending point: 0.000 (ideal)`
107			`= Slack (critical) : 0.559`
108
109			`Number of logic level(s): 0`
110			`Starting point: DDwD_Top.ascii_reg[0] / Q`
111			`Ending point: DDwD_Top.ascii_reg[0] / D`
112			`The start point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
113			`The end point is clocked by DisplayDriverWrapper\|clk [rising] on pin CK`
114
115			`Instance / Net Pin Pin Arrival No. of`
116			`Name Type Name Dir Delay Time Fan Out(s)`
117			`---------------------------------------------------------------------------------------`
118			`DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.597 0.597 -`
119			`ascii_reg[0] Net - - - - 1`
120			`DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.597 -`
121			`=======================================================================================`
122
123
124
125			`##### END OF TIMING REPORT #####]`
126
127			`Constraints that could not be applied`
128			`None`

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [impl1_fpga_mapper.srr_Min] - Blame information for rev 5