Subversion Repositories single-14-segment-display-driver-w-decoder

##### START OF TIMING REPORT #####[

# Timing Report written on Tue Jan 17 23:41:24 2017

#

Top view:               DisplayDriverWrapper

Requested Frequency:    433.9 MHz

Wire load mode:         top

Paths requested:        5

Constraint File(s):

@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.

Performance Summary

*******************

Worst slack in design: 0.439

                             Requested     Estimated     Requested     Estimated                Clock        Clock

Starting Clock               Frequency     Frequency     Period        Period        Slack      Type         Group

----------------------------------------------------------------------------------------------------------------------------------

DisplayDriverWrapper|clk     433.9 MHz     368.8 MHz     2.305         2.712         -0.407     inferred     Autoconstr_clkgroup_0

==================================================================================================================================

Clock Relationships

*******************

Clocks                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise

------------------------------------------------------------------------------------------------------------------------------------------

Starting                  Ending                    |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack

------------------------------------------------------------------------------------------------------------------------------------------

DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  0.000       0.439  |  No paths    -      |  No paths    -      |  No paths    -

==========================================================================================================================================

 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.

       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

Interface Information

*********************

No IO constraint found

====================================

Detailed Report for Clock: DisplayDriverWrapper|clk

====================================

Starting Points with Worst Slack

********************************

                           Starting                                                                  Arrival

Instance                   Reference                    Type         Pin     Net                     Time        Slack

                           Clock

----------------------------------------------------------------------------------------------------------------------

bttn_state_fifo[1]         DisplayDriverWrapper|clk     FD1S3JX      Q       bttn_state_fifo[1]      0.587       0.439

bttn_state_fifo[2]         DisplayDriverWrapper|clk     FD1S3JX      Q       bttn_state_fifo[2]      0.587       0.439

bttn_state_fifo_0io[0]     DisplayDriverWrapper|clk     IFS1P3JX     Q       bttn_state_fifo[0]      0.587       0.439

symbol_scan_cntr[7]        DisplayDriverWrapper|clk     FD1P3DX      Q       symbol_scan_cntr[7]     0.559       0.884

symbol_scan_cntr[0]        DisplayDriverWrapper|clk     FD1P3DX      Q       symbol_scan_cntr[0]     0.653       0.979

symbol_scan_cntr[1]        DisplayDriverWrapper|clk     FD1P3DX      Q       symbol_scan_cntr[1]     0.653       0.979

symbol_scan_cntr[2]        DisplayDriverWrapper|clk     FD1P3DX      Q       symbol_scan_cntr[2]     0.653       0.979

symbol_scan_cntr[3]        DisplayDriverWrapper|clk     FD1P3DX      Q       symbol_scan_cntr[3]     0.653       0.979

symbol_scan_cntr[4]        DisplayDriverWrapper|clk     FD1P3DX      Q       symbol_scan_cntr[4]     0.653       0.979

symbol_scan_cntr[5]        DisplayDriverWrapper|clk     FD1P3DX      Q       symbol_scan_cntr[5]     0.653       0.979

======================================================================================================================

Ending Points with Worst Slack

******************************

                        Starting                                                                             Required

Instance                Reference                    Type        Pin     Net                                 Time         Slack

                        Clock

-------------------------------------------------------------------------------------------------------------------------------

bttn_state_fifo[1]      DisplayDriverWrapper|clk     FD1S3JX     D       bttn_state_fifo[0]                  0.148        0.439

bttn_state_fifo[2]      DisplayDriverWrapper|clk     FD1S3JX     D       bttn_state_fifo[1]                  0.148        0.439

bttn_state_fifo[3]      DisplayDriverWrapper|clk     FD1S3JX     D       bttn_state_fifo[2]                  0.148        0.439

bttn_state              DisplayDriverWrapper|clk     FD1S3AX     D       bttn_stateand                       0.148        0.679

symbol_scan_cntr[7]     DisplayDriverWrapper|clk     FD1P3DX     D       symbol_scan_cntr_s[7]               0.148        0.884

symbol_scan_cntr[0]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933

symbol_scan_cntr[1]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933

symbol_scan_cntr[2]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933

symbol_scan_cntr[3]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933

symbol_scan_cntr[4]     DisplayDriverWrapper|clk     FD1P3DX     SP      bttn_state_fifo_0io_RNIB9K02[0]     0.128        0.933

===============================================================================================================================

Worst Path Information

***********************

Path information for path number 1:

    Propagation time:                        0.587

    + Clock delay at starting point:         0.000 (ideal)

    - Requested Period:                      0.000

    - Hold time:                             0.148

    - Clock delay at ending point:           0.000 (ideal)

    = Slack (critical) :                     0.439

    Number of logic level(s):                0

    Starting point:                          bttn_state_fifo[1] / Q

    Ending point:                            bttn_state_fifo[2] / D

    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK

    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK

Instance / Net                     Pin      Pin               Arrival     No. of

Name                   Type        Name     Dir     Delay     Time        Fan Out(s)

------------------------------------------------------------------------------------

bttn_state_fifo[1]     FD1S3JX     Q        Out     0.587     0.587       -

bttn_state_fifo[1]     Net         -        -       -         -           3

bttn_state_fifo[2]     FD1S3JX     D        In      0.000     0.587       -

====================================================================================

##### END OF TIMING REPORT #####]

Constraints that could not be applied

None