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liubenoff |
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@A: MF827 |No constraint file specified.
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@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Clock Summary
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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-----------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
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=====================================================================================================
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@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":75:4:75:5|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sun Jan 08 00:49:34 2017
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###########################################################]
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