URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [report/] [DisplayDriverwDecoder_impl1_fpga_mapper_combined_clk.rpt] - Blame information for rev 9

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@S |Clock Optimization Summary
 
 
#### START OF CLOCK OPTIMIZATION REPORT #####[
 
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
 
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
 
=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
@K:CKID0001       clk                 port                   13         bttn_state
=======================================================================================
 
 
##### END OF CLOCK OPTIMIZATION REPORT ######]
 

Line No.	Rev	Author	Line
1	5	liubenoff
2
3			`@S \|Clock Optimization Summary`
4
5
6			`#### START OF CLOCK OPTIMIZATION REPORT #####[`
7
8	9	liubenoff	`1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)`
9	5	liubenoff
10	9	liubenoff	`8 instances converted, 0 sequential instances remain driven by gated/generated clocks`
11	5	liubenoff
12	9	liubenoff	`=========================== Non-Gated/Non-Generated Clocks ============================`
13			`Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance`
14			`---------------------------------------------------------------------------------------`
15			`@K:CKID0001 clk port 13 bttn_state`
16			`=======================================================================================`
17	5	liubenoff
18
19			`##### END OF CLOCK OPTIMIZATION REPORT ######]`
20

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [report/] [DisplayDriverwDecoder_impl1_fpga_mapper_combined_clk.rpt] - Blame information for rev 9