Subversion Repositories single-14-segment-display-driver-w-decoder

@N: MF248 |Running in 64-bit mode.

@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

@N: MT206 |Auto Constrain mode is enabled

@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.

@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed

@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi

@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF

@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.

@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.