URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synlog/] [report/] [impl1_fpga_mapper_combined_clk.rpt] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	liubenoff
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3			`@S \|Clock Optimization Summary`
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6			`#### START OF CLOCK OPTIMIZATION REPORT #####[`
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8			`1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)`
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12			`============================== Non-Gated/Non-Generated Clocks ===============================`
13			`Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance`
14			`---------------------------------------------------------------------------------------------`
15			`@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]`
16			`=============================================================================================`
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19			`##### END OF CLOCK OPTIMIZATION REPORT ######]`
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