URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synthesis_lse.html] - Blame information for rev 5

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<HTML>
<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>
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<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild  Report</big></U></B>
synthesis:  version Diamond (64-bit) 3.8.0.115.3
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Sun Jan 08 00:19:59 2017
 
 
Command Line:  synthesis -f DisplayDriverwDecoder_impl1_lattice.synproj -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
 
Synthesis options:
The -a option is ECP5U.
The -s option is 6.
The -t option is CABGA381.
The -d option is LFE5U-45F.
Using package CABGA381.
Using performance grade 6.
 
 
##########################################################
 
### Lattice Family : ECP5U
 
### Device  : LFE5U-45F
 
### Package : CABGA381
 
### Speed   : 6
 
##########################################################
 
 
 
Optimization goal = Timing
Top-level module name = DisplayDriverWrapper.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1
 
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO
 
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
 
ROM style = auto
RAM style = auto
The -comp option is FALSE.
 
-p C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data (searchpath added)
-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1 (searchpath added)
-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build (searchpath added)
VHDL library = work
VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd
VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd
NGD file = DisplayDriverwDecoder_impl1.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...
 
Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482
Compile design.
Compile Design Begin
INFO - synthesis: The default VHDL library search path is now "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1". VHDL-1504
 
INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16): analyzing entity displaydriverwdecoder_top. VHDL-1012
INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50): analyzing architecture arch. VHDL-1010
unit DisplayDriverWrapper is not yet analyzed. VHDL-1485
Analyzing VHDL file c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd. VHDL-1481
INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): analyzing entity displaydriverwrapper. VHDL-1012
 
unit DisplayDriverWrapper is not yet analyzed. VHDL-1485
unit DisplayDriverWrapper is not yet analyzed. VHDL-1485
c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): executing DisplayDriverWrapper(arch)
 
WARNING - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31): replacing existing netlist DisplayDriverWrapper(arch). VHDL-1205
Top module name (VHDL): DisplayDriverWrapper
 
 
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
 
Loading device for application map from file 'sa5p45.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.38.
Top-level module name = DisplayDriverWrapper.
######## Missing driver on net disp_data[13]. Patching with GND.
######## Missing driver on net disp_data[12]. Patching with GND.
######## Missing driver on net disp_data[11]. Patching with GND.
######## Missing driver on net disp_data[10]. Patching with GND.
 
 
######## Missing driver on net disp_data[7]. Patching with GND.
 
######## Missing driver on net disp_data[5]. Patching with GND.
 
######## Missing driver on net disp_data[3]. Patching with GND.
 
######## Missing driver on net disp_data[1]. Patching with GND.
 
 
 
 
 
 
 
WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in DisplayDriverWrapper_drc.log.
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data/sa5plib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...
WARNING - synthesis: logical net 'clk' has no load.
WARNING - synthesis: input pad net 'clk' has no legal load.
WARNING - synthesis: logical net 'reset' has no load.
WARNING - synthesis: input pad net 'reset' has no legal load.
WARNING - synthesis: logical net 'button' has no load.
 
WARNING - synthesis: DRC complete with 6 warnings.
All blocks are expanded and NGD expansion is successful.
Writing NGD file DisplayDriverwDecoder_impl1.ngd.
 
################### Begin Area Report (DisplayDriverWrapper)######################
Number of register bits => 0 of 44457 (0 % )
 
OB => 15
################### End Area Report ##################
 
################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 0
Clock Enable Nets
Number of Clock Enables: 0
Top 0 highest fanout Clock Enables:
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : disp_data[0], loads : 0
  Net : disp_data[1], loads : 0
  Net : disp_data[2], loads : 0
  Net : disp_data[3], loads : 0
  Net : disp_data[4], loads : 0
  Net : disp_data[5], loads : 0
  Net : disp_data[6], loads : 0
  Net : disp_data[7], loads : 0
  Net : disp_data[8], loads : 0
 
################### End Clock Report ##################
 
Peak Memory Usage: 99.668  MB
 
--------------------------------------------------------------
Elapsed CPU time for LSE flow : 1.156  secs
--------------------------------------------------------------
 
 
 
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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [synthesis_lse.html] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	liubenoff	`<HTML>`
2			`<HEAD><TITLE>Synthesis and Ngdbuild Report</TITLE>`
3			`<STYLE TYPE="text/css">`
4			`<!--`
5			body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; }
6			`-->`
7			`</STYLE>`
8			`</HEAD>`
9			`<PRE><A name="Syn"></A><B><U><big>Synthesis and Ngdbuild Report</big></U></B>`
10			`synthesis: version Diamond (64-bit) 3.8.0.115.3`
11
12			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
13			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
14			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
15			`Copyright (c) 2001 Agere Systems All rights reserved.`
16			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.`
17			`Sun Jan 08 00:19:59 2017`
18
19
20			`Command Line: synthesis -f DisplayDriverwDecoder_impl1_lattice.synproj -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml`
21
22			`Synthesis options:`
23			`The -a option is ECP5U.`
24			`The -s option is 6.`
25			`The -t option is CABGA381.`
26			`The -d option is LFE5U-45F.`
27			`Using package CABGA381.`
28			`Using performance grade 6.`
29
30
31			`##########################################################`
32
33			`### Lattice Family : ECP5U`
34
35			`### Device : LFE5U-45F`
36
37			`### Package : CABGA381`
38
39			`### Speed : 6`
40
41			`##########################################################`
42
43
44
45			`Optimization goal = Timing`
46			`Top-level module name = DisplayDriverWrapper.`
47			`Target frequency = 200.000000 MHz.`
48			`Maximum fanout = 1000.`
49			`Timing path count = 3`
50			`BRAM utilization = 100.000000 %`
51			`DSP usage = true`
52			`DSP utilization = 100.000000 %`
53			`fsm_encoding_style = auto`
54			`resolve_mixed_drivers = 0`
55			`fix_gated_clocks = 1`
56
57			`Mux style = Auto`
58			`Use Carry Chain = true`
59			`carry_chain_length = 0`
60			`Loop Limit = 1950.`
61			`Use IO Insertion = TRUE`
62			`Use IO Reg = AUTO`
63
64			`Resource Sharing = TRUE`
65			`Propagate Constants = TRUE`
66			`Remove Duplicate Registers = TRUE`
67
68			`ROM style = auto`
69			`RAM style = auto`
70			`The -comp option is FALSE.`
71
72			`-p C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data (searchpath added)`
73			`-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1 (searchpath added)`
74			`-p C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build (searchpath added)`
75			`VHDL library = work`
76			`VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverwDecoder_Top.vhd`
77			`VHDL design file = C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/DisplayDriverWrapper.vhd`
78			`NGD file = DisplayDriverwDecoder_impl1.ngd`
79			`-sdc option: SDC file input not used.`
80			`-lpf option: Output file option is ON.`
81			`Hardtimer checking is enabled (default). The -dt option is not used.`
82			`The -r option is OFF. [ Remove LOC Properties is OFF. ]`
83			`Technology check ok...`
84
85			`Analyzing Verilog file C:/lscc/diamond/3.8_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/ecp5u.v. VERI-1482`
86			`Compile design.`
87			`Compile Design Begin`
88			`INFO - synthesis: The default VHDL library search path is now "C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1". VHDL-1504`
89
90			`INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16): analyzing entity displaydriverwdecoder_top. VHDL-1012`
91			`INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50): analyzing architecture arch. VHDL-1010`
92			`unit DisplayDriverWrapper is not yet analyzed. VHDL-1485`
93			`Analyzing VHDL file c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd. VHDL-1481`
94			`INFO - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): analyzing entity displaydriverwrapper. VHDL-1012`
95
96			`unit DisplayDriverWrapper is not yet analyzed. VHDL-1485`
97			`unit DisplayDriverWrapper is not yet analyzed. VHDL-1485`
98			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): executing DisplayDriverWrapper(arch)`
99
100			`WARNING - synthesis: c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31): replacing existing netlist DisplayDriverWrapper(arch). VHDL-1205`
101			`Top module name (VHDL): DisplayDriverWrapper`
102
103
104			`Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...`
105
106			`Loading device for application map from file 'sa5p45.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.`
107			`Package Status: Final Version 1.38.`
108			`Top-level module name = DisplayDriverWrapper.`
109			`######## Missing driver on net disp_data[13]. Patching with GND.`
110			`######## Missing driver on net disp_data[12]. Patching with GND.`
111			`######## Missing driver on net disp_data[11]. Patching with GND.`
112			`######## Missing driver on net disp_data[10]. Patching with GND.`
113
114
115			`######## Missing driver on net disp_data[7]. Patching with GND.`
116
117			`######## Missing driver on net disp_data[5]. Patching with GND.`
118
119			`######## Missing driver on net disp_data[3]. Patching with GND.`
120
121			`######## Missing driver on net disp_data[1]. Patching with GND.`
122
123
124
125
126
127
128
129			`WARNING - synthesis: No user .sdc file.`
130			`Results of NGD DRC are available in DisplayDriverWrapper_drc.log.`
131			`Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/sa5p00/data/sa5plib.ngl'...`
132			`Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/xo2c00/data/xo2clib.ngl'...`
133			`Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/mg5g00/data/mg5glib.ngl'...`
134			`Loading NGL library 'C:/lscc/diamond/3.8_x64/ispfpga/or5g00/data/orc5glib.ngl'...`
135			`WARNING - synthesis: logical net 'clk' has no load.`
136			`WARNING - synthesis: input pad net 'clk' has no legal load.`
137			`WARNING - synthesis: logical net 'reset' has no load.`
138			`WARNING - synthesis: input pad net 'reset' has no legal load.`
139			`WARNING - synthesis: logical net 'button' has no load.`
140
141			`WARNING - synthesis: DRC complete with 6 warnings.`
142			`All blocks are expanded and NGD expansion is successful.`
143			`Writing NGD file DisplayDriverwDecoder_impl1.ngd.`
144
145			`################### Begin Area Report (DisplayDriverWrapper)######################`
146			`Number of register bits => 0 of 44457 (0 % )`
147
148			`OB => 15`
149			`################### End Area Report ##################`
150
151			`################### Begin Clock Report ######################`
152			`Clock Nets`
153			`Number of Clocks: 0`
154			`Clock Enable Nets`
155			`Number of Clock Enables: 0`
156			`Top 0 highest fanout Clock Enables:`
157			`Highest fanout non-clock nets`
158			`Top 10 highest fanout non-clock nets:`
159			`Net : disp_data[0], loads : 0`
160			`Net : disp_data[1], loads : 0`
161			`Net : disp_data[2], loads : 0`
162			`Net : disp_data[3], loads : 0`
163			`Net : disp_data[4], loads : 0`
164			`Net : disp_data[5], loads : 0`
165			`Net : disp_data[6], loads : 0`
166			`Net : disp_data[7], loads : 0`
167			`Net : disp_data[8], loads : 0`
168
169			`################### End Clock Report ##################`
170
171			`Peak Memory Usage: 99.668 MB`
172
173			`--------------------------------------------------------------`
174			`Elapsed CPU time for LSE flow : 1.156 secs`
175			`--------------------------------------------------------------`
176
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