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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [syntmp/] [DisplayDriverwDecoder_impl1_srr.htm] - Blame information for rev 5

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1 5 liubenoff 
<html><body><samp><pre>
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<!@TC:1484261677>
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Fri Jan 13 00:54:37 2017
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#Implementation: impl1
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<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
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@N: : <!@TM:1484261677> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
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@N: : <!@TM:1484261677> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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20 
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484261677> | Setting time resolution to ns
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@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484261677> | Top entity is set to DisplayDriverWrapper.
22 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
23 
VHDL syntax check successful!
24 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
25 
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1484261677> | Synthesizing work.displaydriverwrapper.arch.
26 
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:38:11:38:16:@W:CD638:@XP_MSG">DisplayDriverWrapper.vhd(38)</a><!@TM:1484261677> | Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</font>
27 
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1484261677> | Synthesizing work.displaydriverwdecoder_top.arch.
28 
Post processing for work.displaydriverwdecoder_top.arch
29 
Post processing for work.displaydriverwrapper.arch
30 
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:20:8:20:14:@N:CL159:@XP_MSG">DisplayDriverWrapper.vhd(20)</a><!@TM:1484261677> | Input button is unused.
31 
 
32 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
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34 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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36 
Process completed successfully.
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# Fri Jan 13 00:54:37 2017
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39 
###########################################################]
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<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
41 
@N: : <!@TM:1484261677> | Running in 64-bit mode
42 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
43 
 
44 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
45 
 
46 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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48 
Process completed successfully.
49 
# Fri Jan 13 00:54:37 2017
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51 
###########################################################]
52 
@END
53 
 
54 
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
55 
 
56 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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58 
Process completed successfully.
59 
# Fri Jan 13 00:54:37 2017
60 
 
61 
###########################################################]
62 
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
63 
@N: : <!@TM:1484261679> | Running in 64-bit mode
64 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
65 
 
66 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
67 
 
68 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
69 
 
70 
Process completed successfully.
71 
# Fri Jan 13 00:54:39 2017
72 
 
73 
###########################################################]
74 
Pre-mapping Report
75 
 
76 
<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31</a>
77 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
78 
Product Version L-2016.03L-1
79 
 
80 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
81 
 
82 
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484261679> | No constraint file specified.
83 
Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt:@XP_FILE">DisplayDriverwDecoder_impl1_scck.rpt</a>
84 
Printing clock  summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
85 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484261679> | Running in 64-bit mode.
86 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484261679> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
87 
 
88 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
89 
 
90 
 
91 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
92 
 
93 
 
94 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
95 
 
96 
 
97 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
98 
 
99 
ICG Latch Removal Summary:
100 
Number of ICG latches removed:  0
101 
Number of ICG latches not removed:      0
102 
syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper
103 
 
104 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
105 
 
106 
 
107 
 
108 
<a name=mapperReport6></a>Clock Summary</a>
109 
*****************
110 
 
111 
Start                        Requested     Requested     Clock        Clock                     Clock
112 
Clock                        Frequency     Period        Type         Group                     Load
113 
-----------------------------------------------------------------------------------------------------
114 
DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8
115 
=====================================================================================================
116 
 
117 
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd:76:8:76:10:@W:MT529:@XP_MSG">displaydriverwdecoder_top.vhd(76)</a><!@TM:1484261679> | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
118 
 
119 
Finished Pre Mapping Phase.
120 
 
121 
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
122 
 
123 
None
124 
None
125 
 
126 
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
127 
 
128 
Pre-mapping successful!
129 
 
130 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
131 
 
132 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
133 
# Fri Jan 13 00:54:39 2017
134 
 
135 
###########################################################]
136 
Map & Optimize Report
137 
 
138 
<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31</a>
139 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
140 
Product Version L-2016.03L-1
141 
 
142 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
143 
 
144 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484261682> | Running in 64-bit mode.
145 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484261682> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
146 
 
147 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
148 
 
149 
 
150 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
151 
 
152 
 
153 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
154 
 
155 
 
156 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
157 
 
158 
 
159 
 
160 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
161 
 
162 
 
163 
Available hyper_sources - for debug and ip models
164 
        None Found
165 
 
166 
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484261682> | Auto Constrain mode is enabled
167 
 
168 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
169 
 
170 
 
171 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
172 
 
173 
 
174 
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
175 
 
176 
 
177 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
178 
 
179 
 
180 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
181 
 
182 
 
183 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
184 
 
185 
 
186 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
187 
 
188 
 
189 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
190 
 
191 
 
192 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
193 
 
194 
 
195 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
196 
 
197 
Pass             CPU time               Worst Slack             Luts / Registers
198 
------------------------------------------------------------
199 
 
200 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
201 
 
202 
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484261682> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
203 
 
204 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
205 
 
206 
 
207 
 
208 
@S |Clock Optimization Summary
209 
 
210 
 
211 
<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
212 
 
213 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
214 
 
215 
 
216 
 
217 
============================== Non-Gated/Non-Generated Clocks ===============================
218 
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
219 
---------------------------------------------------------------------------------------------
220 
<a href="@|S:clk@|E:DDwD_Top.ascii_reg[6]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       clk                 port                   8          DDwD_Top.ascii_reg[6]
221 
=============================================================================================
222 
 
223 
 
224 
##### END OF CLOCK OPTIMIZATION REPORT ######]
225 
 
226 
 
227 
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
228 
 
229 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
230 
 
231 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
232 
 
233 
Writing EDIF Netlist and constraint files
234 
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484261682> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
235 
L-2016.03L-1
236 
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484261682> | Synplicity Constraint File capacitance units using default value of 1pF
237 
 
238 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
239 
 
240 
 
241 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
242 
 
243 
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484261682> | Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"</font>
244 
 
245 
 
246 
<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
247 
# Timing Report written on Fri Jan 13 00:54:42 2017
248 
#
249 
 
250 
 
251 
Top view:               DisplayDriverWrapper
252 
Requested Frequency:    1220.4 MHz
253 
Wire load mode:         top
254 
Paths requested:        5
255 
Constraint File(s):
256 
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484261682> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
257 
 
258 
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484261682> | Clock constraints cover only FF-to-FF paths associated with the clock.
259 
 
260 
 
261 
 
262 
<a name=performanceSummary10></a>Performance Summary</a>
263 
*******************
264 
 
265 
 
266 
Worst slack in design: -0.145
267 
 
268 
                             Requested      Estimated      Requested     Estimated                Clock        Clock
269 
Starting Clock               Frequency      Frequency      Period        Period        Slack      Type         Group
270 
------------------------------------------------------------------------------------------------------------------------------------
271 
DisplayDriverWrapper|clk     1220.4 MHz     1037.3 MHz     0.819         0.964         -0.145     inferred     Autoconstr_clkgroup_0
272 
====================================================================================================================================
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274 
 
275 
 
276 
 
277 
 
278 
<a name=clockRelationships11></a>Clock Relationships</a>
279 
*******************
280 
 
281 
Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
282 
-------------------------------------------------------------------------------------------------------------------------------------------
283 
Starting                  Ending                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
284 
-------------------------------------------------------------------------------------------------------------------------------------------
285 
DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  0.819       -0.145  |  No paths    -      |  No paths    -      |  No paths    -
286 
===========================================================================================================================================
287 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
288 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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290 
 
291 
 
292 
<a name=interfaceInfo12></a>Interface Information </a>
293 
*********************
294 
 
295 
No IO constraint found
296 
 
297 
 
298 
 
299 
====================================
300 
<a name=clockReport13></a>Detailed Report for Clock: DisplayDriverWrapper|clk</a>
301 
====================================
302 
 
303 
 
304 
 
305 
<a name=startingSlack14></a>Starting Points with Worst Slack</a>
306 
********************************
307 
 
308 
                          Starting                                                          Arrival
309 
Instance                  Reference                    Type        Pin     Net              Time        Slack
310 
                          Clock
311 
--------------------------------------------------------------------------------------------------------------
312 
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[0]     0.753       -0.145
313 
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[1]     0.753       -0.145
314 
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[2]     0.753       -0.145
315 
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[3]     0.753       -0.145
316 
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[4]     0.753       -0.145
317 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[5]     0.753       -0.145
318 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[6]     0.753       -0.145
319 
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[7]     0.753       -0.145
320 
==============================================================================================================
321 
 
322 
 
323 
<a name=endingSlack15></a>Ending Points with Worst Slack</a>
324 
******************************
325 
 
326 
                          Starting                                                          Required
327 
Instance                  Reference                    Type        Pin     Net              Time         Slack
328 
                          Clock
329 
---------------------------------------------------------------------------------------------------------------
330 
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[0]     0.608        -0.145
331 
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[1]     0.608        -0.145
332 
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[2]     0.608        -0.145
333 
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[3]     0.608        -0.145
334 
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[4]     0.608        -0.145
335 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[5]     0.608        -0.145
336 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[6]     0.608        -0.145
337 
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[7]     0.608        -0.145
338 
===============================================================================================================
339 
 
340 
 
341 
 
342 
<a name=worstPaths16></a>Worst Path Information</a>
343 
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srs:fp:20159:20426:@XP_NAMES_GATE">View Worst Path in Analyst</a>
344 
***********************
345 
 
346 
 
347 
Path information for path number 1:
348 
      Requested Period:                      0.819
349 
    - Setup time:                            0.211
350 
    + Clock delay at ending point:           0.000 (ideal)
351 
    = Required time:                         0.608
352 
 
353 
    - Propagation time:                      0.753
354 
    - Clock delay at starting point:         0.000 (ideal)
355 
    = Slack (critical) :                     -0.145
356 
 
357 
    Number of logic level(s):                0
358 
    Starting point:                          DDwD_Top.ascii_reg[0] / Q
359 
    Ending point:                            DDwD_Top.ascii_reg[0] / D
360 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
361 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
362 
 
363 
Instance / Net                        Pin      Pin               Arrival     No. of
364 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
365 
---------------------------------------------------------------------------------------
366 
DDwD_Top.ascii_reg[0]     FD1S3IX     Q        Out     0.753     0.753       -
367 
ascii_reg[0]              Net         -        -       -         -           1
368 
DDwD_Top.ascii_reg[0]     FD1S3IX     D        In      0.000     0.753       -
369 
=======================================================================================
370 
 
371 
 
372 
Path information for path number 2:
373 
      Requested Period:                      0.819
374 
    - Setup time:                            0.211
375 
    + Clock delay at ending point:           0.000 (ideal)
376 
    = Required time:                         0.608
377 
 
378 
    - Propagation time:                      0.753
379 
    - Clock delay at starting point:         0.000 (ideal)
380 
    = Slack (critical) :                     -0.145
381 
 
382 
    Number of logic level(s):                0
383 
    Starting point:                          DDwD_Top.ascii_reg[1] / Q
384 
    Ending point:                            DDwD_Top.ascii_reg[1] / D
385 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
386 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
387 
 
388 
Instance / Net                        Pin      Pin               Arrival     No. of
389 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
390 
---------------------------------------------------------------------------------------
391 
DDwD_Top.ascii_reg[1]     FD1S3JX     Q        Out     0.753     0.753       -
392 
ascii_reg[1]              Net         -        -       -         -           1
393 
DDwD_Top.ascii_reg[1]     FD1S3JX     D        In      0.000     0.753       -
394 
=======================================================================================
395 
 
396 
 
397 
Path information for path number 3:
398 
      Requested Period:                      0.819
399 
    - Setup time:                            0.211
400 
    + Clock delay at ending point:           0.000 (ideal)
401 
    = Required time:                         0.608
402 
 
403 
    - Propagation time:                      0.753
404 
    - Clock delay at starting point:         0.000 (ideal)
405 
    = Slack (critical) :                     -0.145
406 
 
407 
    Number of logic level(s):                0
408 
    Starting point:                          DDwD_Top.ascii_reg[2] / Q
409 
    Ending point:                            DDwD_Top.ascii_reg[2] / D
410 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
411 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
412 
 
413 
Instance / Net                        Pin      Pin               Arrival     No. of
414 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
415 
---------------------------------------------------------------------------------------
416 
DDwD_Top.ascii_reg[2]     FD1S3IX     Q        Out     0.753     0.753       -
417 
ascii_reg[2]              Net         -        -       -         -           1
418 
DDwD_Top.ascii_reg[2]     FD1S3IX     D        In      0.000     0.753       -
419 
=======================================================================================
420 
 
421 
 
422 
Path information for path number 4:
423 
      Requested Period:                      0.819
424 
    - Setup time:                            0.211
425 
    + Clock delay at ending point:           0.000 (ideal)
426 
    = Required time:                         0.608
427 
 
428 
    - Propagation time:                      0.753
429 
    - Clock delay at starting point:         0.000 (ideal)
430 
    = Slack (critical) :                     -0.145
431 
 
432 
    Number of logic level(s):                0
433 
    Starting point:                          DDwD_Top.ascii_reg[3] / Q
434 
    Ending point:                            DDwD_Top.ascii_reg[3] / D
435 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
436 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
437 
 
438 
Instance / Net                        Pin      Pin               Arrival     No. of
439 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
440 
---------------------------------------------------------------------------------------
441 
DDwD_Top.ascii_reg[3]     FD1S3IX     Q        Out     0.753     0.753       -
442 
ascii_reg[3]              Net         -        -       -         -           1
443 
DDwD_Top.ascii_reg[3]     FD1S3IX     D        In      0.000     0.753       -
444 
=======================================================================================
445 
 
446 
 
447 
Path information for path number 5:
448 
      Requested Period:                      0.819
449 
    - Setup time:                            0.211
450 
    + Clock delay at ending point:           0.000 (ideal)
451 
    = Required time:                         0.608
452 
 
453 
    - Propagation time:                      0.753
454 
    - Clock delay at starting point:         0.000 (ideal)
455 
    = Slack (critical) :                     -0.145
456 
 
457 
    Number of logic level(s):                0
458 
    Starting point:                          DDwD_Top.ascii_reg[4] / Q
459 
    Ending point:                            DDwD_Top.ascii_reg[4] / D
460 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
461 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
462 
 
463 
Instance / Net                        Pin      Pin               Arrival     No. of
464 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
465 
---------------------------------------------------------------------------------------
466 
DDwD_Top.ascii_reg[4]     FD1S3JX     Q        Out     0.753     0.753       -
467 
ascii_reg[4]              Net         -        -       -         -           1
468 
DDwD_Top.ascii_reg[4]     FD1S3JX     D        In      0.000     0.753       -
469 
=======================================================================================
470 
 
471 
 
472 
 
473 
##### END OF TIMING REPORT #####]
474 
 
475 
Constraints that could not be applied
476 
None
477 
 
478 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
479 
 
480 
 
481 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
482 
 
483 
---------------------------------------
484 
<a name=resourceUsage17></a>Resource Usage Report</a>
485 
Part: lfe5um5g_45f-8
486 
 
487 
Register bits: 8 of 43848 (0%)
488 
PIC Latch:       0
489 
I/O cells:       18
490 
 
491 
 
492 
Details:
493 
FD1S3IX:        5
494 
FD1S3JX:        3
495 
GSR:            1
496 
IB:             2
497 
OB:             16
498 
PUR:            1
499 
VHI:            2
500 
VLO:            1
501 
false:          1
502 
Mapper successful!
503 
 
504 
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
505 
 
506 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
507 
# Fri Jan 13 00:54:42 2017
508 
 
509 
###########################################################]
510 
 
511 
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