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<html><body><samp><pre>
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<!@TC:1484694493>
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Wed Jan 18 01:08:13 2017
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#Implementation: impl1
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<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484694493> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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<a name=compilerReport2></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484694493> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484694493> | Setting time resolution to ns
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@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:29:@N::@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484694493> | Top entity is set to display_driver_wrapper.
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File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:29:@N:CD630:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484694493> | Synthesizing work.display_driver_wrapper.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:17:7:17:31:@N:CD630:@XP_MSG">display_driver_w_decoder.vhd(17)</a><!@TM:1484694493> | Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
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<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:42:11:42:20:@W:CD638:@XP_MSG">display_driver_w_decoder.vhd(42)</a><!@TM:1484694493> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:15:7:15:20:@N:CD630:@XP_MSG">ascii_decoder.vhd(15)</a><!@TM:1484694493> | Synthesizing work.ascii_decoder.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd:12:7:12:29:@N:CD630:@XP_MSG">decoder_table_dist_rom.vhd(12)</a><!@TM:1484694493> | Synthesizing work.decoder_table_dist_rom.structure.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484694493> | Synthesizing work.rom128x1a.syn_black_box.
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Post processing for work.rom128x1a.syn_black_box
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Post processing for work.decoder_table_dist_rom.structure
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Post processing for work.ascii_decoder.arch
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Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
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Post processing for work.display_driver_wrapper.arch
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ascii_decoder.vhd(17)</a><!@TM:1484694493> | Input clk is unused.
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ascii_decoder.vhd(18)</a><!@TM:1484694493> | Input reset is unused.
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:23:8:23:13:@N:CL159:@XP_MSG">display_driver_w_decoder.vhd(23)</a><!@TM:1484694493> | Input wr_en is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Jan 18 01:08:13 2017
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###########################################################]
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<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484694493> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Jan 18 01:08:13 2017
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Jan 18 01:08:13 2017
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###########################################################]
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<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484694494> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Jan 18 01:08:14 2017
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###########################################################]
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Pre-mapping Report
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<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484694495> | No constraint file specified.
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Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt:@XP_FILE">DisplayDriverwDecoder_impl1_scck.rpt</a>
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
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@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484694495> | Running in 64-bit mode.
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@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484694495> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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113 |
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syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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<a name=mapperReport6></a>Clock Summary</a>
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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-------------------------------------------------------------------------------------------------------------------------------------------------------------
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display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
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display_driver_wrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
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=============================================================================================================================================================
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<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:52:8:52:10:@W:MT529:@XP_MSG">display_driver_wrapper.vhd(52)</a><!@TM:1484694495> | Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None
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None
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137 |
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Wed Jan 18 01:08:15 2017
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###########################################################]
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Map & Optimize Report
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<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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152 |
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Product Version L-2016.03L-1
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153 |
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154 |
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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156 |
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@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484694497> | Running in 64-bit mode.
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@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484694497> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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161 |
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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163 |
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164 |
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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166 |
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167 |
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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171 |
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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174 |
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Available hyper_sources - for debug and ip models
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176 |
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None Found
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@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484694497> | Auto Constrain mode is enabled
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:74:8:74:10:@N::@XP_MSG">display_driver_wrapper.vhd(74)</a><!@TM:1484694497> | Found counter in view:work.display_driver_wrapper(arch) inst symbol_scan_cntr[7:0]
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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186 |
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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189 |
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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192 |
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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204 |
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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1 0h:00m:00s -0.76ns 6 / 13
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2 0h:00m:00s -0.76ns 6 / 13
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3 0h:00m:00s -0.62ns 7 / 13
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4 0h:00m:00s -0.58ns 6 / 13
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5 |
liubenoff |
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
221 |
|
|
|
222 |
9 |
liubenoff |
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484694497> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
223 |
5 |
liubenoff |
|
224 |
6 |
liubenoff |
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
225 |
5 |
liubenoff |
|
226 |
9 |
liubenoff |
@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1484694497> | Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
|
227 |
5 |
liubenoff |
|
228 |
|
|
|
229 |
|
|
@S |Clock Optimization Summary
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
|
233 |
|
|
|
234 |
9 |
liubenoff |
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
|
235 |
5 |
liubenoff |
|
236 |
9 |
liubenoff |
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
237 |
5 |
liubenoff |
|
238 |
9 |
liubenoff |
=========================== Non-Gated/Non-Generated Clocks ============================
|
239 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
240 |
|
|
---------------------------------------------------------------------------------------
|
241 |
|
|
<a href="@|S:clk@|E:bttn_state@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> clk port 13 bttn_state
|
242 |
|
|
=======================================================================================
|
243 |
5 |
liubenoff |
|
244 |
|
|
|
245 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
246 |
|
|
|
247 |
|
|
|
248 |
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
249 |
|
|
|
250 |
|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
|
251 |
|
|
|
252 |
9 |
liubenoff |
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
|
253 |
5 |
liubenoff |
|
254 |
|
|
Writing EDIF Netlist and constraint files
|
255 |
9 |
liubenoff |
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484694497> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
|
256 |
5 |
liubenoff |
L-2016.03L-1
|
257 |
9 |
liubenoff |
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484694497> | Synplicity Constraint File capacitance units using default value of 1pF
|
258 |
5 |
liubenoff |
|
259 |
9 |
liubenoff |
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
260 |
5 |
liubenoff |
|
261 |
|
|
|
262 |
6 |
liubenoff |
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
263 |
5 |
liubenoff |
|
264 |
9 |
liubenoff |
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484694497> | Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"</font>
|
265 |
5 |
liubenoff |
|
266 |
|
|
|
267 |
|
|
<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
|
268 |
9 |
liubenoff |
# Timing Report written on Wed Jan 18 01:08:17 2017
|
269 |
5 |
liubenoff |
#
|
270 |
|
|
|
271 |
|
|
|
272 |
9 |
liubenoff |
Top view: display_driver_wrapper
|
273 |
|
|
Requested Frequency: 433.9 MHz
|
274 |
5 |
liubenoff |
Wire load mode: top
|
275 |
|
|
Paths requested: 5
|
276 |
|
|
Constraint File(s):
|
277 |
9 |
liubenoff |
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484694497> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
278 |
5 |
liubenoff |
|
279 |
9 |
liubenoff |
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484694497> | Clock constraints cover only FF-to-FF paths associated with the clock.
|
280 |
5 |
liubenoff |
|
281 |
|
|
|
282 |
|
|
|
283 |
|
|
<a name=performanceSummary10></a>Performance Summary</a>
|
284 |
|
|
*******************
|
285 |
|
|
|
286 |
|
|
|
287 |
9 |
liubenoff |
Worst slack in design: -0.407
|
288 |
5 |
liubenoff |
|
289 |
9 |
liubenoff |
Requested Estimated Requested Estimated Clock Clock
|
290 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
291 |
|
|
------------------------------------------------------------------------------------------------------------------------------------
|
292 |
|
|
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
|
293 |
|
|
====================================================================================================================================
|
294 |
5 |
liubenoff |
|
295 |
|
|
|
296 |
|
|
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
<a name=clockRelationships11></a>Clock Relationships</a>
|
300 |
|
|
*******************
|
301 |
|
|
|
302 |
9 |
liubenoff |
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
303 |
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------
|
304 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
305 |
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------
|
306 |
|
|
display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
|
307 |
|
|
===============================================================================================================================================
|
308 |
5 |
liubenoff |
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
309 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
310 |
|
|
|
311 |
|
|
|
312 |
|
|
|
313 |
|
|
<a name=interfaceInfo12></a>Interface Information </a>
|
314 |
|
|
*********************
|
315 |
|
|
|
316 |
|
|
No IO constraint found
|
317 |
|
|
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
====================================
|
321 |
9 |
liubenoff |
<a name=clockReport13></a>Detailed Report for Clock: display_driver_wrapper|clk</a>
|
322 |
5 |
liubenoff |
====================================
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
<a name=startingSlack14></a>Starting Points with Worst Slack</a>
|
327 |
|
|
********************************
|
328 |
|
|
|
329 |
9 |
liubenoff |
Starting Arrival
|
330 |
|
|
Instance Reference Type Pin Net Time Slack
|
331 |
|
|
Clock
|
332 |
|
|
---------------------------------------------------------------------------------------------------------------------
|
333 |
|
|
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
|
334 |
|
|
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
|
335 |
|
|
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
|
336 |
|
|
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
|
337 |
|
|
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
|
338 |
|
|
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
|
339 |
|
|
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
|
340 |
|
|
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
|
341 |
|
|
bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
|
342 |
|
|
bttn_state_fifo[1] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
|
343 |
|
|
=====================================================================================================================
|
344 |
5 |
liubenoff |
|
345 |
|
|
|
346 |
|
|
<a name=endingSlack15></a>Ending Points with Worst Slack</a>
|
347 |
|
|
******************************
|
348 |
|
|
|
349 |
9 |
liubenoff |
Starting Required
|
350 |
|
|
Instance Reference Type Pin Net Time Slack
|
351 |
|
|
Clock
|
352 |
|
|
----------------------------------------------------------------------------------------------------------------------------------
|
353 |
|
|
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
|
354 |
|
|
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
|
355 |
|
|
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
|
356 |
|
|
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
|
357 |
|
|
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
|
358 |
|
|
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
|
359 |
|
|
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
|
360 |
|
|
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
361 |
|
|
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
362 |
|
|
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
363 |
|
|
==================================================================================================================================
|
364 |
5 |
liubenoff |
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
<a name=worstPaths16></a>Worst Path Information</a>
|
368 |
9 |
liubenoff |
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.srs:fp:23312:24986:@XP_NAMES_GATE">View Worst Path in Analyst</a>
|
369 |
5 |
liubenoff |
***********************
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
Path information for path number 1:
|
373 |
9 |
liubenoff |
Requested Period: 2.305
|
374 |
5 |
liubenoff |
- Setup time: 0.211
|
375 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
376 |
9 |
liubenoff |
= Required time: 2.094
|
377 |
5 |
liubenoff |
|
378 |
9 |
liubenoff |
- Propagation time: 2.501
|
379 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
380 |
9 |
liubenoff |
= Slack (critical) : -0.407
|
381 |
5 |
liubenoff |
|
382 |
9 |
liubenoff |
Number of logic level(s): 5
|
383 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
384 |
6 |
liubenoff |
Ending point: symbol_scan_cntr[7] / D
|
385 |
9 |
liubenoff |
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
386 |
|
|
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
387 |
5 |
liubenoff |
|
388 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
389 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
390 |
|
|
-------------------------------------------------------------------------------------------
|
391 |
9 |
liubenoff |
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
392 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
393 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
394 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
395 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
396 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
397 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
398 |
6 |
liubenoff |
symbol_scan_cntr_cry[2] Net - - - - 1
|
399 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
400 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
401 |
6 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
402 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
403 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
404 |
6 |
liubenoff |
symbol_scan_cntr_cry[6] Net - - - - 1
|
405 |
9 |
liubenoff |
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
406 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
407 |
6 |
liubenoff |
symbol_scan_cntr_s[7] Net - - - - 1
|
408 |
9 |
liubenoff |
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
409 |
6 |
liubenoff |
===========================================================================================
|
410 |
5 |
liubenoff |
|
411 |
|
|
|
412 |
|
|
Path information for path number 2:
|
413 |
9 |
liubenoff |
Requested Period: 2.305
|
414 |
5 |
liubenoff |
- Setup time: 0.211
|
415 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
416 |
9 |
liubenoff |
= Required time: 2.094
|
417 |
5 |
liubenoff |
|
418 |
6 |
liubenoff |
- Propagation time: 2.442
|
419 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
420 |
9 |
liubenoff |
= Slack (non-critical) : -0.348
|
421 |
5 |
liubenoff |
|
422 |
6 |
liubenoff |
Number of logic level(s): 4
|
423 |
9 |
liubenoff |
Starting point: symbol_scan_cntr[1] / Q
|
424 |
6 |
liubenoff |
Ending point: symbol_scan_cntr[7] / D
|
425 |
9 |
liubenoff |
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
426 |
|
|
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
427 |
5 |
liubenoff |
|
428 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
429 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
430 |
|
|
-------------------------------------------------------------------------------------------
|
431 |
9 |
liubenoff |
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
432 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
433 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
434 |
6 |
liubenoff |
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
435 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
436 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
437 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
438 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
439 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
440 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
441 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
442 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
443 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
444 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
445 |
9 |
liubenoff |
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
446 |
6 |
liubenoff |
===========================================================================================
|
447 |
5 |
liubenoff |
|
448 |
|
|
|
449 |
|
|
Path information for path number 3:
|
450 |
9 |
liubenoff |
Requested Period: 2.305
|
451 |
5 |
liubenoff |
- Setup time: 0.211
|
452 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
453 |
9 |
liubenoff |
= Required time: 2.094
|
454 |
5 |
liubenoff |
|
455 |
9 |
liubenoff |
- Propagation time: 2.442
|
456 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
457 |
9 |
liubenoff |
= Slack (non-critical) : -0.348
|
458 |
5 |
liubenoff |
|
459 |
9 |
liubenoff |
Number of logic level(s): 4
|
460 |
|
|
Starting point: symbol_scan_cntr[2] / Q
|
461 |
6 |
liubenoff |
Ending point: symbol_scan_cntr[7] / D
|
462 |
9 |
liubenoff |
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
463 |
|
|
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
464 |
5 |
liubenoff |
|
465 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
466 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
467 |
|
|
-------------------------------------------------------------------------------------------
|
468 |
9 |
liubenoff |
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
469 |
|
|
symbol_scan_cntr[2] Net - - - - 15
|
470 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
471 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
472 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
473 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
474 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
475 |
6 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
476 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
477 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
478 |
6 |
liubenoff |
symbol_scan_cntr_cry[6] Net - - - - 1
|
479 |
9 |
liubenoff |
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
480 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
481 |
6 |
liubenoff |
symbol_scan_cntr_s[7] Net - - - - 1
|
482 |
9 |
liubenoff |
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
483 |
6 |
liubenoff |
===========================================================================================
|
484 |
5 |
liubenoff |
|
485 |
|
|
|
486 |
|
|
Path information for path number 4:
|
487 |
9 |
liubenoff |
Requested Period: 2.305
|
488 |
5 |
liubenoff |
- Setup time: 0.211
|
489 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
490 |
9 |
liubenoff |
= Required time: 2.094
|
491 |
5 |
liubenoff |
|
492 |
9 |
liubenoff |
- Propagation time: 2.442
|
493 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
494 |
9 |
liubenoff |
= Slack (non-critical) : -0.348
|
495 |
5 |
liubenoff |
|
496 |
9 |
liubenoff |
Number of logic level(s): 4
|
497 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
498 |
|
|
Ending point: symbol_scan_cntr[5] / D
|
499 |
|
|
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
500 |
|
|
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
501 |
5 |
liubenoff |
|
502 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
503 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
504 |
|
|
-------------------------------------------------------------------------------------------
|
505 |
9 |
liubenoff |
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
506 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
507 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
508 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
509 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
510 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
511 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
512 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
513 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
514 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
515 |
6 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
516 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
517 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
518 |
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
519 |
|
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
520 |
6 |
liubenoff |
===========================================================================================
|
521 |
5 |
liubenoff |
|
522 |
|
|
|
523 |
|
|
Path information for path number 5:
|
524 |
9 |
liubenoff |
Requested Period: 2.305
|
525 |
5 |
liubenoff |
- Setup time: 0.211
|
526 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
527 |
9 |
liubenoff |
= Required time: 2.094
|
528 |
5 |
liubenoff |
|
529 |
9 |
liubenoff |
- Propagation time: 2.442
|
530 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
531 |
9 |
liubenoff |
= Slack (non-critical) : -0.348
|
532 |
5 |
liubenoff |
|
533 |
9 |
liubenoff |
Number of logic level(s): 4
|
534 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
535 |
|
|
Ending point: symbol_scan_cntr[6] / D
|
536 |
|
|
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
537 |
|
|
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
538 |
5 |
liubenoff |
|
539 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
540 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
541 |
|
|
-------------------------------------------------------------------------------------------
|
542 |
9 |
liubenoff |
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
543 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
544 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
545 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
546 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
547 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
548 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
549 |
6 |
liubenoff |
symbol_scan_cntr_cry[2] Net - - - - 1
|
550 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
551 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
552 |
6 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
553 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
554 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
555 |
|
|
symbol_scan_cntr_s[6] Net - - - - 1
|
556 |
|
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
557 |
6 |
liubenoff |
===========================================================================================
|
558 |
5 |
liubenoff |
|
559 |
|
|
|
560 |
|
|
|
561 |
|
|
##### END OF TIMING REPORT #####]
|
562 |
|
|
|
563 |
|
|
Constraints that could not be applied
|
564 |
|
|
None
|
565 |
|
|
|
566 |
6 |
liubenoff |
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
567 |
5 |
liubenoff |
|
568 |
|
|
|
569 |
6 |
liubenoff |
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
570 |
5 |
liubenoff |
|
571 |
|
|
---------------------------------------
|
572 |
|
|
<a name=resourceUsage17></a>Resource Usage Report</a>
|
573 |
|
|
Part: lfe5um5g_45f-8
|
574 |
|
|
|
575 |
9 |
liubenoff |
Register bits: 13 of 43848 (0%)
|
576 |
5 |
liubenoff |
PIC Latch: 0
|
577 |
|
|
I/O cells: 18
|
578 |
|
|
|
579 |
|
|
|
580 |
|
|
Details:
|
581 |
6 |
liubenoff |
CCU2C: 5
|
582 |
9 |
liubenoff |
FD1P3DX: 8
|
583 |
|
|
FD1S3AX: 1
|
584 |
|
|
FD1S3JX: 3
|
585 |
5 |
liubenoff |
GSR: 1
|
586 |
9 |
liubenoff |
IB: 3
|
587 |
|
|
IFS1P3JX: 1
|
588 |
|
|
INV: 2
|
589 |
|
|
OB: 15
|
590 |
|
|
ORCALUT4: 4
|
591 |
5 |
liubenoff |
PUR: 1
|
592 |
6 |
liubenoff |
ROM128X1A: 14
|
593 |
|
|
VHI: 1
|
594 |
5 |
liubenoff |
VLO: 1
|
595 |
|
|
Mapper successful!
|
596 |
|
|
|
597 |
6 |
liubenoff |
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
598 |
5 |
liubenoff |
|
599 |
6 |
liubenoff |
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
600 |
9 |
liubenoff |
# Wed Jan 18 01:08:17 2017
|
601 |
5 |
liubenoff |
|
602 |
|
|
###########################################################]
|
603 |
|
|
|
604 |
|
|
</pre></samp></body></html>
|