URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [syntmp/] [impl1_premap_warnings_txt_report.htm] - Blame information for rev 6

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<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:54:4:54:6:@W:MT529:@XP_MSG">displaydriverwrapper.vhd(54)</a><!@TM:0> | Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
 
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Line No.	Rev	Author	Line
1	6	liubenoff	`<html><body><samp><pre>`
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3			`<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd:54:4:54:6:@W:MT529:@XP_MSG">displaydriverwrapper.vhd(54)</a><!@TM:0> \| Found inferred clock DisplayDriverWrapper\|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>`
4
5			`</pre></samp></body></html>`

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [syntmp/] [impl1_premap_warnings_txt_report.htm] - Blame information for rev 6