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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [syntmp/] [impl1_srr.htm] - Blame information for rev 5

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1 5 liubenoff 
<html><body><samp><pre>
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<!@TC:1483829372>
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Sun Jan 08 00:49:32 2017
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#Implementation: impl1
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<a name=compilerReport14></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
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@N: : <!@TM:1483829372> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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<a name=compilerReport15></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
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@N: : <!@TM:1483829372> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1483829372> | Setting time resolution to ns
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@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N::@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Top entity is set to DisplayDriverWrapper.
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Synthesizing work.displaydriverwrapper.arch.
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<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:38:11:38:16:@W:CD638:@XP_MSG">DisplayDriverWrapper.vhd(38)</a><!@TM:1483829372> | Signal empty is undriven. Either assign the signal a value or remove the signal declaration.</font>
27 
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:16:7:16:32:@N:CD630:@XP_MSG">DisplayDriverwDecoder_Top.vhd(16)</a><!@TM:1483829372> | Synthesizing work.displaydriverwdecoder_top.arch.
28 
Post processing for work.displaydriverwdecoder_top.arch
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<font color=#A52A2A>@W:<a href="@W:CL240:@XP_HELP">CL240</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd:38:8:38:17:@W:CL240:@XP_MSG">DisplayDriverwDecoder_Top.vhd(38)</a><!@TM:1483829372> | disp_data is not assigned a value (floating) -- simulation mismatch possible. </font>
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Post processing for work.displaydriverwrapper.arch
31 
@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:20:8:20:14:@N:CL159:@XP_MSG">DisplayDriverWrapper.vhd(20)</a><!@TM:1483829372> | Input button is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sun Jan 08 00:49:32 2017
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###########################################################]
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<a name=compilerReport16></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
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@N: : <!@TM:1483829372> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Selected library: work cell: DisplayDriverWrapper view arch as top level
45 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829372> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sun Jan 08 00:49:32 2017
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sun Jan 08 00:49:32 2017
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###########################################################]
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<a name=compilerReport17></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016</a>
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@N: : <!@TM:1483829374> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829374> | Selected library: work cell: DisplayDriverWrapper view arch as top level
69 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">DisplayDriverWrapper.vhd(15)</a><!@TM:1483829374> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Sun Jan 08 00:49:34 2017
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###########################################################]
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Pre-mapping Report
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<a name=mapperReport18></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31</a>
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
83 
Product Version L-2016.03L-1
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85 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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87 
@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1483829374> | No constraint file specified.
88 
Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt:@XP_FILE">impl1_scck.rpt</a>
89 
Printing clock  summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
90 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1483829374> | Running in 64-bit mode.
91 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1483829374> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
92 
 
93 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
94 
 
95 
 
96 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
97 
 
98 
 
99 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
100 
 
101 
 
102 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
103 
 
104 
ICG Latch Removal Summary:
105 
Number of ICG latches removed:  0
106 
Number of ICG latches not removed:      0
107 
syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
110 
 
111 
 
112 
 
113 
<a name=mapperReport19></a>Clock Summary</a>
114 
*****************
115 
 
116 
Start                        Requested     Requested     Clock        Clock                     Clock
117 
Clock                        Frequency     Period        Type         Group                     Load
118 
-----------------------------------------------------------------------------------------------------
119 
DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8
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=====================================================================================================
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122 
<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd:75:4:75:6:@W:MT529:@XP_MSG">displaydriverwdecoder_top.vhd(75)</a><!@TM:1483829374> | Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
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Finished Pre Mapping Phase.
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126 
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
127 
 
128 
None
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None
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131 
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
132 
 
133 
Pre-mapping successful!
134 
 
135 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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137 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
138 
# Sun Jan 08 00:49:34 2017
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140 
###########################################################]
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Map & Optimize Report
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143 
<a name=mapperReport20></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31</a>
144 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
145 
Product Version L-2016.03L-1
146 
 
147 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
148 
 
149 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1483829376> | Running in 64-bit mode.
150 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1483829376> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
151 
 
152 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
153 
 
154 
 
155 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
156 
 
157 
 
158 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
159 
 
160 
 
161 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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163 
 
164 
 
165 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
166 
 
167 
 
168 
Available hyper_sources - for debug and ip models
169 
        None Found
170 
 
171 
@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1483829376> | Auto Constrain mode is enabled
172 
 
173 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
174 
 
175 
 
176 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
177 
 
178 
 
179 
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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181 
 
182 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
183 
 
184 
 
185 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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187 
 
188 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
189 
 
190 
 
191 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
192 
 
193 
 
194 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
195 
 
196 
 
197 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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199 
 
200 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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202 
Pass             CPU time               Worst Slack             Luts / Registers
203 
------------------------------------------------------------
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205 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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207 
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1483829376> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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213 
@S |Clock Optimization Summary
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216 
<a name=clockReport21></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
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218 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
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221 
 
222 
============================== Non-Gated/Non-Generated Clocks ===============================
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Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
224 
---------------------------------------------------------------------------------------------
225 
<a href="@|S:clk@|E:DDwD_Top.ascii_reg[6]@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001  @XP_NAMES_BY_PROP">ClockId0001 </a>       clk                 port                   8          DDwD_Top.ascii_reg[6]
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=============================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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232 
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
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234 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
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236 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
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238 
Writing EDIF Netlist and constraint files
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@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1483829376> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
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L-2016.03L-1
241 
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1483829376> | Synplicity Constraint File capacitance units using default value of 1pF
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243 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
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246 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
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<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1483829376> | Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk"</font>
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<a name=timingReport22></a>##### START OF TIMING REPORT #####[</a>
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# Timing Report written on Sun Jan 08 00:49:36 2017
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#
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256 
Top view:               DisplayDriverWrapper
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Requested Frequency:    1297.0 MHz
258 
Wire load mode:         top
259 
Paths requested:        5
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Constraint File(s):
261 
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1483829376> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
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@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1483829376> | Clock constraints cover only FF-to-FF paths associated with the clock.
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267 
<a name=performanceSummary23></a>Performance Summary</a>
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*******************
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271 
Worst slack in design: -0.136
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273 
                             Requested      Estimated      Requested     Estimated                Clock        Clock
274 
Starting Clock               Frequency      Frequency      Period        Period        Slack      Type         Group
275 
------------------------------------------------------------------------------------------------------------------------------------
276 
DisplayDriverWrapper|clk     1297.0 MHz     1102.5 MHz     0.771         0.907         -0.136     inferred     Autoconstr_clkgroup_0
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====================================================================================================================================
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283 
<a name=clockRelationships24></a>Clock Relationships</a>
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*******************
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286 
Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
287 
-------------------------------------------------------------------------------------------------------------------------------------------
288 
Starting                  Ending                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
289 
-------------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  0.771       -0.136  |  No paths    -      |  No paths    -      |  No paths    -
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===========================================================================================================================================
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 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
293 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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297 
<a name=interfaceInfo25></a>Interface Information </a>
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*********************
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300 
No IO constraint found
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304 
====================================
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<a name=clockReport26></a>Detailed Report for Clock: DisplayDriverWrapper|clk</a>
306 
====================================
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310 
<a name=startingSlack27></a>Starting Points with Worst Slack</a>
311 
********************************
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313 
                          Starting                                                          Arrival
314 
Instance                  Reference                    Type        Pin     Net              Time        Slack
315 
                          Clock
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--------------------------------------------------------------------------------------------------------------
317 
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[0]     0.853       -0.136
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DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[1]     0.853       -0.136
319 
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[2]     0.853       -0.136
320 
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[3]     0.853       -0.136
321 
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[4]     0.853       -0.136
322 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[5]     0.853       -0.136
323 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[6]     0.853       -0.136
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DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[7]     0.853       -0.136
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==============================================================================================================
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328 
<a name=endingSlack28></a>Ending Points with Worst Slack</a>
329 
******************************
330 
 
331 
                          Starting                                                          Required
332 
Instance                  Reference                    Type        Pin     Net              Time         Slack
333 
                          Clock
334 
---------------------------------------------------------------------------------------------------------------
335 
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[0]     0.717        -0.136
336 
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[1]     0.717        -0.136
337 
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[2]     0.717        -0.136
338 
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[3]     0.717        -0.136
339 
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[4]     0.717        -0.136
340 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[5]     0.717        -0.136
341 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[6]     0.717        -0.136
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DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[7]     0.717        -0.136
343 
===============================================================================================================
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346 
 
347 
<a name=worstPaths29></a>Worst Path Information</a>
348 
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srs:fp:21030:21297:@XP_NAMES_GATE">View Worst Path in Analyst</a>
349 
***********************
350 
 
351 
 
352 
Path information for path number 1:
353 
      Requested Period:                      0.771
354 
    - Setup time:                            0.054
355 
    + Clock delay at ending point:           0.000 (ideal)
356 
    = Required time:                         0.717
357 
 
358 
    - Propagation time:                      0.853
359 
    - Clock delay at starting point:         0.000 (ideal)
360 
    = Slack (critical) :                     -0.136
361 
 
362 
    Number of logic level(s):                0
363 
    Starting point:                          DDwD_Top.ascii_reg[0] / Q
364 
    Ending point:                            DDwD_Top.ascii_reg[0] / D
365 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
366 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
367 
 
368 
Instance / Net                        Pin      Pin               Arrival     No. of
369 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
370 
---------------------------------------------------------------------------------------
371 
DDwD_Top.ascii_reg[0]     FD1S3IX     Q        Out     0.853     0.853       -
372 
ascii_reg[0]              Net         -        -       -         -           1
373 
DDwD_Top.ascii_reg[0]     FD1S3IX     D        In      0.000     0.853       -
374 
=======================================================================================
375 
 
376 
 
377 
Path information for path number 2:
378 
      Requested Period:                      0.771
379 
    - Setup time:                            0.054
380 
    + Clock delay at ending point:           0.000 (ideal)
381 
    = Required time:                         0.717
382 
 
383 
    - Propagation time:                      0.853
384 
    - Clock delay at starting point:         0.000 (ideal)
385 
    = Slack (critical) :                     -0.136
386 
 
387 
    Number of logic level(s):                0
388 
    Starting point:                          DDwD_Top.ascii_reg[1] / Q
389 
    Ending point:                            DDwD_Top.ascii_reg[1] / D
390 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
391 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
392 
 
393 
Instance / Net                        Pin      Pin               Arrival     No. of
394 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
395 
---------------------------------------------------------------------------------------
396 
DDwD_Top.ascii_reg[1]     FD1S3JX     Q        Out     0.853     0.853       -
397 
ascii_reg[1]              Net         -        -       -         -           1
398 
DDwD_Top.ascii_reg[1]     FD1S3JX     D        In      0.000     0.853       -
399 
=======================================================================================
400 
 
401 
 
402 
Path information for path number 3:
403 
      Requested Period:                      0.771
404 
    - Setup time:                            0.054
405 
    + Clock delay at ending point:           0.000 (ideal)
406 
    = Required time:                         0.717
407 
 
408 
    - Propagation time:                      0.853
409 
    - Clock delay at starting point:         0.000 (ideal)
410 
    = Slack (critical) :                     -0.136
411 
 
412 
    Number of logic level(s):                0
413 
    Starting point:                          DDwD_Top.ascii_reg[2] / Q
414 
    Ending point:                            DDwD_Top.ascii_reg[2] / D
415 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
416 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
417 
 
418 
Instance / Net                        Pin      Pin               Arrival     No. of
419 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
420 
---------------------------------------------------------------------------------------
421 
DDwD_Top.ascii_reg[2]     FD1S3IX     Q        Out     0.853     0.853       -
422 
ascii_reg[2]              Net         -        -       -         -           1
423 
DDwD_Top.ascii_reg[2]     FD1S3IX     D        In      0.000     0.853       -
424 
=======================================================================================
425 
 
426 
 
427 
Path information for path number 4:
428 
      Requested Period:                      0.771
429 
    - Setup time:                            0.054
430 
    + Clock delay at ending point:           0.000 (ideal)
431 
    = Required time:                         0.717
432 
 
433 
    - Propagation time:                      0.853
434 
    - Clock delay at starting point:         0.000 (ideal)
435 
    = Slack (critical) :                     -0.136
436 
 
437 
    Number of logic level(s):                0
438 
    Starting point:                          DDwD_Top.ascii_reg[3] / Q
439 
    Ending point:                            DDwD_Top.ascii_reg[3] / D
440 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
441 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
442 
 
443 
Instance / Net                        Pin      Pin               Arrival     No. of
444 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
445 
---------------------------------------------------------------------------------------
446 
DDwD_Top.ascii_reg[3]     FD1S3IX     Q        Out     0.853     0.853       -
447 
ascii_reg[3]              Net         -        -       -         -           1
448 
DDwD_Top.ascii_reg[3]     FD1S3IX     D        In      0.000     0.853       -
449 
=======================================================================================
450 
 
451 
 
452 
Path information for path number 5:
453 
      Requested Period:                      0.771
454 
    - Setup time:                            0.054
455 
    + Clock delay at ending point:           0.000 (ideal)
456 
    = Required time:                         0.717
457 
 
458 
    - Propagation time:                      0.853
459 
    - Clock delay at starting point:         0.000 (ideal)
460 
    = Slack (critical) :                     -0.136
461 
 
462 
    Number of logic level(s):                0
463 
    Starting point:                          DDwD_Top.ascii_reg[4] / Q
464 
    Ending point:                            DDwD_Top.ascii_reg[4] / D
465 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
466 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
467 
 
468 
Instance / Net                        Pin      Pin               Arrival     No. of
469 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
470 
---------------------------------------------------------------------------------------
471 
DDwD_Top.ascii_reg[4]     FD1S3JX     Q        Out     0.853     0.853       -
472 
ascii_reg[4]              Net         -        -       -         -           1
473 
DDwD_Top.ascii_reg[4]     FD1S3JX     D        In      0.000     0.853       -
474 
=======================================================================================
475 
 
476 
 
477 
 
478 
##### END OF TIMING REPORT #####]
479 
 
480 
Constraints that could not be applied
481 
None
482 
 
483 
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
484 
 
485 
 
486 
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
487 
 
488 
---------------------------------------
489 
<a name=resourceUsage30></a>Resource Usage Report</a>
490 
Part: lfe5u_45f-6
491 
 
492 
Register bits: 8 of 43848 (0%)
493 
PIC Latch:       0
494 
I/O cells:       17
495 
 
496 
 
497 
Details:
498 
FD1S3IX:        5
499 
FD1S3JX:        3
500 
GSR:            1
501 
IB:             2
502 
OB:             15
503 
PUR:            1
504 
VHI:            2
505 
VLO:            1
506 
false:          1
507 
Mapper successful!
508 
 
509 
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
510 
 
511 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
512 
# Sun Jan 08 00:49:36 2017
513 
 
514 
###########################################################]
515 
 
516 
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