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<html><body><samp><pre>
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<!@TC:1484689279>
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Tue Jan 17 23:41:19 2017
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#Implementation: impl1
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<a name=compilerReport9></a>Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484689280> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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<a name=compilerReport10></a>Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484689280> | Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1484689280> | Setting time resolution to ns
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@N: : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N::@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Top entity is set to DisplayDriverWrapper.
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File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
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VHDL syntax check successful!
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:CD630:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Synthesizing work.displaydriverwrapper.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:17:7:17:31:@N:CD630:@XP_MSG">display_driver_w_decoder.vhd(17)</a><!@TM:1484689280> | Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
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<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:47:11:47:20:@W:CD638:@XP_MSG">display_driver_w_decoder.vhd(47)</a><!@TM:1484689280> | Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.</font>
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:15:7:15:19:@N:CD630:@XP_MSG">ascii_decoder.vhd(15)</a><!@TM:1484689280> | Synthesizing work.asciidecoder.arch.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd:12:7:12:26:@N:CD630:@XP_MSG">DistRomAsciiDecoder.vhd(12)</a><!@TM:1484689280> | Synthesizing work.distromasciidecoder.structure.
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@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd:801:10:801:19:@N:CD630:@XP_MSG">ecp5um.vhd(801)</a><!@TM:1484689280> | Synthesizing work.rom128x1a.syn_black_box.
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Post processing for work.rom128x1a.syn_black_box
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Post processing for work.distromasciidecoder.structure
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Post processing for work.asciidecoder.arch
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Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
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Post processing for work.displaydriverwrapper.arch
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:17:8:17:11:@N:CL159:@XP_MSG">ascii_decoder.vhd(17)</a><!@TM:1484689280> | Input clk is unused.
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd:18:8:18:13:@N:CL159:@XP_MSG">ascii_decoder.vhd(18)</a><!@TM:1484689280> | Input reset is unused.
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@N:<a href="@N:CL159:@XP_HELP">CL159</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd:23:8:23:13:@N:CL159:@XP_MSG">display_driver_w_decoder.vhd(23)</a><!@TM:1484689280> | Input wr_en is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Jan 17 23:41:20 2017
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###########################################################]
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<a name=compilerReport11></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484689280> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689280> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Jan 17 23:41:20 2017
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Jan 17 23:41:20 2017
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###########################################################]
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<a name=compilerReport12></a>Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016</a>
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@N: : <!@TM:1484689281> | Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689281> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd:15:7:15:27:@N:NF107:@XP_MSG">display_driver_wrapper.vhd(15)</a><!@TM:1484689281> | Selected library: work cell: DisplayDriverWrapper view arch as top level
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Jan 17 23:41:21 2017
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###########################################################]
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Pre-mapping Report
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<a name=mapperReport13></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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| 92 |
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1484689282> | No constraint file specified.
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Linked File: <a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt:@XP_FILE">impl1_scck.rpt</a>
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
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@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484689282> | Running in 64-bit mode.
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@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484689282> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
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| 113 |
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ICG Latch Removal Summary:
|
| 114 |
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Number of ICG latches removed: 0
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| 115 |
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Number of ICG latches not removed: 0
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| 116 |
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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<a name=mapperReport14></a>Clock Summary</a>
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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---------------------------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper|clk) Autoconstr_clkgroup_0 8
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DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
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=========================================================================================================================================================
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<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:57:4:57:6:@W:MT529:@XP_MSG">display_driver_wrapper.vhd(57)</a><!@TM:1484689282> | Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Jan 17 23:41:22 2017
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###########################################################]
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Map & Optimize Report
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<a name=mapperReport15></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31</a>
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| 154 |
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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| 155 |
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Product Version L-2016.03L-1
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| 156 |
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1484689284> | Running in 64-bit mode.
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@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1484689284> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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| 176 |
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Available hyper_sources - for debug and ip models
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None Found
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@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1484689284> | Auto Constrain mode is enabled
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: : <a href="c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd:77:4:77:6:@N::@XP_MSG">display_driver_wrapper.vhd(77)</a><!@TM:1484689284> | Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 200 |
|
|
|
| 201 |
|
|
|
| 202 |
6 |
liubenoff |
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
| 203 |
5 |
liubenoff |
|
| 204 |
|
|
|
| 205 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 206 |
|
|
|
| 207 |
|
|
|
| 208 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 209 |
|
|
|
| 210 |
|
|
|
| 211 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 212 |
|
|
|
| 213 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 214 |
|
|
------------------------------------------------------------
|
| 215 |
6 |
liubenoff |
1 0h:00m:00s -0.76ns 6 / 13
|
| 216 |
|
|
2 0h:00m:00s -0.76ns 6 / 13
|
| 217 |
5 |
liubenoff |
|
| 218 |
6 |
liubenoff |
3 0h:00m:00s -0.62ns 7 / 13
|
| 219 |
|
|
|
| 220 |
|
|
|
| 221 |
|
|
4 0h:00m:00s -0.58ns 6 / 13
|
| 222 |
|
|
|
| 223 |
5 |
liubenoff |
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 224 |
|
|
|
| 225 |
9 |
liubenoff |
@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1484689284> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
| 226 |
5 |
liubenoff |
|
| 227 |
6 |
liubenoff |
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
| 228 |
5 |
liubenoff |
|
| 229 |
9 |
liubenoff |
@N:<a href="@N:MT611:@XP_HELP">MT611</a> : <!@TM:1484689284> | Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
|
| 230 |
5 |
liubenoff |
|
| 231 |
|
|
|
| 232 |
|
|
@S |Clock Optimization Summary
|
| 233 |
|
|
|
| 234 |
|
|
|
| 235 |
6 |
liubenoff |
<a name=clockReport16></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>
|
| 236 |
5 |
liubenoff |
|
| 237 |
6 |
liubenoff |
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
|
| 238 |
5 |
liubenoff |
|
| 239 |
6 |
liubenoff |
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
| 240 |
5 |
liubenoff |
|
| 241 |
6 |
liubenoff |
=========================== Non-Gated/Non-Generated Clocks ============================
|
| 242 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
| 243 |
|
|
---------------------------------------------------------------------------------------
|
| 244 |
|
|
<a href="@|S:clk@|E:bttn_state@|F:@syn_sample_clock_path==CKID0001@|M:ClockId0001 @XP_NAMES_BY_PROP">ClockId0001 </a> clk port 13 bttn_state
|
| 245 |
|
|
=======================================================================================
|
| 246 |
5 |
liubenoff |
|
| 247 |
|
|
|
| 248 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
| 249 |
|
|
|
| 250 |
|
|
|
| 251 |
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
| 252 |
|
|
|
| 253 |
|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
|
| 254 |
|
|
|
| 255 |
6 |
liubenoff |
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 256 |
5 |
liubenoff |
|
| 257 |
|
|
Writing EDIF Netlist and constraint files
|
| 258 |
9 |
liubenoff |
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1484689284> | Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
|
| 259 |
5 |
liubenoff |
L-2016.03L-1
|
| 260 |
9 |
liubenoff |
@N:<a href="@N:BW106:@XP_HELP">BW106</a> : <!@TM:1484689284> | Synplicity Constraint File capacitance units using default value of 1pF
|
| 261 |
5 |
liubenoff |
|
| 262 |
9 |
liubenoff |
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
| 263 |
5 |
liubenoff |
|
| 264 |
|
|
|
| 265 |
6 |
liubenoff |
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
| 266 |
5 |
liubenoff |
|
| 267 |
9 |
liubenoff |
<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1484689284> | Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"</font>
|
| 268 |
5 |
liubenoff |
|
| 269 |
|
|
|
| 270 |
6 |
liubenoff |
<a name=timingReport17></a>##### START OF TIMING REPORT #####[</a>
|
| 271 |
9 |
liubenoff |
# Timing Report written on Tue Jan 17 23:41:24 2017
|
| 272 |
5 |
liubenoff |
#
|
| 273 |
|
|
|
| 274 |
|
|
|
| 275 |
|
|
Top view: DisplayDriverWrapper
|
| 276 |
6 |
liubenoff |
Requested Frequency: 433.9 MHz
|
| 277 |
5 |
liubenoff |
Wire load mode: top
|
| 278 |
|
|
Paths requested: 5
|
| 279 |
|
|
Constraint File(s):
|
| 280 |
9 |
liubenoff |
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1484689284> | Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
| 281 |
5 |
liubenoff |
|
| 282 |
9 |
liubenoff |
@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1484689284> | Clock constraints cover only FF-to-FF paths associated with the clock.
|
| 283 |
5 |
liubenoff |
|
| 284 |
|
|
|
| 285 |
|
|
|
| 286 |
6 |
liubenoff |
<a name=performanceSummary18></a>Performance Summary</a>
|
| 287 |
5 |
liubenoff |
*******************
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
6 |
liubenoff |
Worst slack in design: -0.407
|
| 291 |
5 |
liubenoff |
|
| 292 |
6 |
liubenoff |
Requested Estimated Requested Estimated Clock Clock
|
| 293 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
| 294 |
|
|
----------------------------------------------------------------------------------------------------------------------------------
|
| 295 |
|
|
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
|
| 296 |
|
|
==================================================================================================================================
|
| 297 |
5 |
liubenoff |
|
| 298 |
|
|
|
| 299 |
|
|
|
| 300 |
|
|
|
| 301 |
|
|
|
| 302 |
6 |
liubenoff |
<a name=clockRelationships19></a>Clock Relationships</a>
|
| 303 |
5 |
liubenoff |
*******************
|
| 304 |
|
|
|
| 305 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
| 306 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
| 307 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
| 308 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
| 309 |
6 |
liubenoff |
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
|
| 310 |
5 |
liubenoff |
===========================================================================================================================================
|
| 311 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
| 312 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 313 |
|
|
|
| 314 |
|
|
|
| 315 |
|
|
|
| 316 |
6 |
liubenoff |
<a name=interfaceInfo20></a>Interface Information </a>
|
| 317 |
5 |
liubenoff |
*********************
|
| 318 |
|
|
|
| 319 |
|
|
No IO constraint found
|
| 320 |
|
|
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
====================================
|
| 324 |
6 |
liubenoff |
<a name=clockReport21></a>Detailed Report for Clock: DisplayDriverWrapper|clk</a>
|
| 325 |
5 |
liubenoff |
====================================
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
|
| 329 |
6 |
liubenoff |
<a name=startingSlack22></a>Starting Points with Worst Slack</a>
|
| 330 |
5 |
liubenoff |
********************************
|
| 331 |
|
|
|
| 332 |
6 |
liubenoff |
Starting Arrival
|
| 333 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 334 |
|
|
Clock
|
| 335 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
| 336 |
|
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
|
| 337 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
|
| 338 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
|
| 339 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
|
| 340 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
|
| 341 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
|
| 342 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
|
| 343 |
|
|
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
|
| 344 |
|
|
bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
|
| 345 |
|
|
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
|
| 346 |
|
|
===================================================================================================================
|
| 347 |
5 |
liubenoff |
|
| 348 |
|
|
|
| 349 |
6 |
liubenoff |
<a name=endingSlack23></a>Ending Points with Worst Slack</a>
|
| 350 |
5 |
liubenoff |
******************************
|
| 351 |
|
|
|
| 352 |
6 |
liubenoff |
Starting Required
|
| 353 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 354 |
|
|
Clock
|
| 355 |
|
|
--------------------------------------------------------------------------------------------------------------------------------
|
| 356 |
|
|
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
|
| 357 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
|
| 358 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
|
| 359 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
|
| 360 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
|
| 361 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
|
| 362 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
|
| 363 |
|
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
| 364 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
| 365 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
| 366 |
|
|
================================================================================================================================
|
| 367 |
5 |
liubenoff |
|
| 368 |
|
|
|
| 369 |
|
|
|
| 370 |
6 |
liubenoff |
<a name=worstPaths24></a>Worst Path Information</a>
|
| 371 |
9 |
liubenoff |
<a href="C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srr:srsfC:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.srs:fp:23703:25377:@XP_NAMES_GATE">View Worst Path in Analyst</a>
|
| 372 |
5 |
liubenoff |
***********************
|
| 373 |
|
|
|
| 374 |
|
|
|
| 375 |
|
|
Path information for path number 1:
|
| 376 |
6 |
liubenoff |
Requested Period: 2.305
|
| 377 |
|
|
- Setup time: 0.211
|
| 378 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 379 |
6 |
liubenoff |
= Required time: 2.094
|
| 380 |
5 |
liubenoff |
|
| 381 |
6 |
liubenoff |
- Propagation time: 2.501
|
| 382 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 383 |
6 |
liubenoff |
= Slack (critical) : -0.407
|
| 384 |
5 |
liubenoff |
|
| 385 |
6 |
liubenoff |
Number of logic level(s): 5
|
| 386 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
| 387 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
| 388 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 389 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 390 |
|
|
|
| 391 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 392 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 393 |
|
|
-------------------------------------------------------------------------------------------
|
| 394 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
| 395 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
| 396 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
| 397 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
| 398 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
| 399 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
| 400 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
| 401 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 402 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
| 403 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
| 404 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 405 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
| 406 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
| 407 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 408 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
| 409 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
| 410 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 411 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
| 412 |
|
|
===========================================================================================
|
| 413 |
5 |
liubenoff |
|
| 414 |
|
|
|
| 415 |
|
|
Path information for path number 2:
|
| 416 |
6 |
liubenoff |
Requested Period: 2.305
|
| 417 |
|
|
- Setup time: 0.211
|
| 418 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 419 |
6 |
liubenoff |
= Required time: 2.094
|
| 420 |
5 |
liubenoff |
|
| 421 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 422 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 423 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 424 |
5 |
liubenoff |
|
| 425 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 426 |
|
|
Starting point: symbol_scan_cntr[1] / Q
|
| 427 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
| 428 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 429 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 430 |
|
|
|
| 431 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 432 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 433 |
|
|
-------------------------------------------------------------------------------------------
|
| 434 |
|
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
| 435 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
| 436 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
| 437 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
| 438 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 439 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
| 440 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
| 441 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 442 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
| 443 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
| 444 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 445 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
| 446 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
| 447 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 448 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
| 449 |
|
|
===========================================================================================
|
| 450 |
5 |
liubenoff |
|
| 451 |
|
|
|
| 452 |
|
|
Path information for path number 3:
|
| 453 |
6 |
liubenoff |
Requested Period: 2.305
|
| 454 |
|
|
- Setup time: 0.211
|
| 455 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 456 |
6 |
liubenoff |
= Required time: 2.094
|
| 457 |
5 |
liubenoff |
|
| 458 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 459 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 460 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 461 |
5 |
liubenoff |
|
| 462 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 463 |
|
|
Starting point: symbol_scan_cntr[2] / Q
|
| 464 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
| 465 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 466 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 467 |
|
|
|
| 468 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 469 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 470 |
|
|
-------------------------------------------------------------------------------------------
|
| 471 |
|
|
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
| 472 |
|
|
symbol_scan_cntr[2] Net - - - - 15
|
| 473 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
| 474 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
| 475 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 476 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
| 477 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
| 478 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 479 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
| 480 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
| 481 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 482 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
| 483 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
| 484 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 485 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
| 486 |
|
|
===========================================================================================
|
| 487 |
5 |
liubenoff |
|
| 488 |
|
|
|
| 489 |
|
|
Path information for path number 4:
|
| 490 |
6 |
liubenoff |
Requested Period: 2.305
|
| 491 |
|
|
- Setup time: 0.211
|
| 492 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 493 |
6 |
liubenoff |
= Required time: 2.094
|
| 494 |
5 |
liubenoff |
|
| 495 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 496 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 497 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 498 |
5 |
liubenoff |
|
| 499 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 500 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
| 501 |
|
|
Ending point: symbol_scan_cntr[5] / D
|
| 502 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 503 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 504 |
|
|
|
| 505 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 506 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 507 |
|
|
-------------------------------------------------------------------------------------------
|
| 508 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
| 509 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
| 510 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
| 511 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
| 512 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
| 513 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
| 514 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
| 515 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 516 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
| 517 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
| 518 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 519 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
| 520 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
| 521 |
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
| 522 |
|
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
| 523 |
|
|
===========================================================================================
|
| 524 |
5 |
liubenoff |
|
| 525 |
|
|
|
| 526 |
|
|
Path information for path number 5:
|
| 527 |
6 |
liubenoff |
Requested Period: 2.305
|
| 528 |
|
|
- Setup time: 0.211
|
| 529 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 530 |
6 |
liubenoff |
= Required time: 2.094
|
| 531 |
5 |
liubenoff |
|
| 532 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 533 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 534 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 535 |
5 |
liubenoff |
|
| 536 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 537 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
| 538 |
|
|
Ending point: symbol_scan_cntr[6] / D
|
| 539 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 540 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 541 |
|
|
|
| 542 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 543 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 544 |
|
|
-------------------------------------------------------------------------------------------
|
| 545 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
| 546 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
| 547 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
| 548 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
| 549 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
| 550 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
| 551 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
| 552 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 553 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
| 554 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
| 555 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 556 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
| 557 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
| 558 |
|
|
symbol_scan_cntr_s[6] Net - - - - 1
|
| 559 |
|
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
| 560 |
|
|
===========================================================================================
|
| 561 |
5 |
liubenoff |
|
| 562 |
|
|
|
| 563 |
|
|
|
| 564 |
|
|
##### END OF TIMING REPORT #####]
|
| 565 |
|
|
|
| 566 |
|
|
Constraints that could not be applied
|
| 567 |
|
|
None
|
| 568 |
|
|
|
| 569 |
6 |
liubenoff |
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
| 570 |
5 |
liubenoff |
|
| 571 |
|
|
|
| 572 |
6 |
liubenoff |
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
| 573 |
5 |
liubenoff |
|
| 574 |
|
|
---------------------------------------
|
| 575 |
6 |
liubenoff |
<a name=resourceUsage25></a>Resource Usage Report</a>
|
| 576 |
|
|
Part: lfe5um5g_45f-8
|
| 577 |
5 |
liubenoff |
|
| 578 |
6 |
liubenoff |
Register bits: 13 of 43848 (0%)
|
| 579 |
5 |
liubenoff |
PIC Latch: 0
|
| 580 |
6 |
liubenoff |
I/O cells: 19
|
| 581 |
5 |
liubenoff |
|
| 582 |
|
|
|
| 583 |
|
|
Details:
|
| 584 |
6 |
liubenoff |
CCU2C: 5
|
| 585 |
|
|
FD1P3DX: 8
|
| 586 |
|
|
FD1S3AX: 1
|
| 587 |
5 |
liubenoff |
FD1S3JX: 3
|
| 588 |
|
|
GSR: 1
|
| 589 |
6 |
liubenoff |
IB: 3
|
| 590 |
|
|
IFS1P3JX: 1
|
| 591 |
|
|
INV: 2
|
| 592 |
|
|
OB: 16
|
| 593 |
|
|
ORCALUT4: 4
|
| 594 |
5 |
liubenoff |
PUR: 1
|
| 595 |
6 |
liubenoff |
ROM128X1A: 14
|
| 596 |
|
|
VHI: 1
|
| 597 |
5 |
liubenoff |
VLO: 1
|
| 598 |
|
|
Mapper successful!
|
| 599 |
|
|
|
| 600 |
6 |
liubenoff |
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
| 601 |
5 |
liubenoff |
|
| 602 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 603 |
9 |
liubenoff |
# Tue Jan 17 23:41:24 2017
|
| 604 |
5 |
liubenoff |
|
| 605 |
|
|
###########################################################]
|
| 606 |
|
|
|
| 607 |
|
|
</pre></samp></body></html>
|
