OpenCores
URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Sources/] [Decoding_Table/] [ROM_ASCII_Decoder/] [decoder_table_dist_rom_impl/] [decoder_table_dist_rom/] [decoder_table_dist_rom.vhd] - Blame information for rev 9

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 9 liubenoff
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.8.0.115.3
2
-- Module  Version: 2.8
3
--C:\lscc\diamond\3.8_x64\ispfpga\bin\nt64\scuba.exe -w -n decoder_table_dist_rom -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00g -type rom -addr_width 7 -num_rows 128 -data_width 14 -outdata UNREGISTERED -memfile c:/projects/single-14-segment-display-driver-w-decoder/project/sources/decoding_table/decoder_table_init_binary.mem -memformat bin -fdc C:/Projects/single-14-segment-display-driver-w-decoder/Project/Sources/Decoding_Table/ROM_ASCII_Decoder/decoder_table_dist_rom_impl/decoder_table_dist_rom/decoder_table_dist_rom.fdc 
4
 
5
-- Wed Jan 18 00:48:29 2017
6
 
7
library IEEE;
8
use IEEE.std_logic_1164.all;
9
library ecp5um;
10
use ecp5um.components.all;
11
 
12
entity decoder_table_dist_rom is
13
    port (
14
        Address: in  std_logic_vector(6 downto 0);
15
        Q: out  std_logic_vector(13 downto 0));
16
end decoder_table_dist_rom;
17
 
18
architecture Structure of decoder_table_dist_rom is
19
 
20
    attribute NGD_DRC_MASK : integer;
21
    attribute NGD_DRC_MASK of Structure : architecture is 1;
22
 
23
begin
24
    -- component instantiation statements
25
    mem_0_13: ROM128X1A
26
        generic map (initval=> X"DA3FFFFFBA3FFFFFB7FE6997BFFFFFFE")
27
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
28
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
29
            AD0=>Address(0), DO0=>Q(13));
30
 
31
    mem_0_12: ROM128X1A
32
        generic map (initval=> X"EDEFFDEBFDEFFDEB7BFFB3E718FFD7FF")
33
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
34
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
35
            AD0=>Address(0), DO0=>Q(12));
36
 
37
    mem_0_11: ROM128X1A
38
        generic map (initval=> X"F679B7FFEE79B7FFEFDFFA97BFFFFFDF")
39
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
40
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
41
            AD0=>Address(0), DO0=>Q(11));
42
 
43
    mem_0_10: ROM128X1A
44
        generic map (initval=> X"F0BFD7FFB8BFD7FFEFFE7A176DFFFFFE")
45
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
46
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
47
            AD0=>Address(0), DO0=>Q(10));
48
 
49
    mem_0_9: ROM128X1A
50
        generic map (initval=> X"EFEFFDEBFFEFFDEAF3FFF3E31AFFD7FF")
51
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
52
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
53
            AD0=>Address(0), DO0=>Q(9));
54
 
55
    mem_0_8: ROM128X1A
56
        generic map (initval=> X"DCFF9FFEECFF9FFFBFFFF9976DFFFFFF")
57
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
58
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
59
            AD0=>Address(0), DO0=>Q(8));
60
 
61
    mem_0_7: ROM128X1A
62
        generic map (initval=> X"9FF2FE59FFF2FE585CA3D3C7D0FFB0A3")
63
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
64
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
65
            AD0=>Address(0), DO0=>Q(7));
66
 
67
    mem_0_6: ROM128X1A
68
        generic map (initval=> X"B7F2F69DFFF2F69DDC8B93C7D0FF388B")
69
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
70
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
71
            AD0=>Address(0), DO0=>Q(6));
72
 
73
    mem_0_5: ROM128X1A
74
        generic map (initval=> X"7F100615F7100614FC8EFFC3E3FF288E")
75
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
76
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
77
            AD0=>Address(0), DO0=>Q(5));
78
 
79
    mem_0_4: ROM128X1A
80
        generic map (initval=> X"3F180215F7180214FEBABFF7EBFF2ABA")
81
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
82
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
83
            AD0=>Address(0), DO0=>Q(4));
84
 
85
    mem_0_3: ROM128X1A
86
        generic map (initval=> X"7BD56B4353D56B42DC92BFA7DAFF8492")
87
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
88
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
89
            AD0=>Address(0), DO0=>Q(3));
90
 
91
    mem_0_2: ROM128X1A
92
        generic map (initval=> X"7F551A69DF551A69FC24FF85FFFFD024")
93
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
94
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
95
            AD0=>Address(0), DO0=>Q(2));
96
 
97
    mem_0_1: ROM128X1A
98
        generic map (initval=> X"3F581AE99F581AE87C60FFF5F7FFD060")
99
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
100
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
101
            AD0=>Address(0), DO0=>Q(1));
102
 
103
    mem_0_0: ROM128X1A
104
        generic map (initval=> X"7BE07F0193E07F007C12FFA7F2FF0012")
105
        port map (AD6=>Address(6), AD5=>Address(5), AD4=>Address(4),
106
            AD3=>Address(3), AD2=>Address(2), AD1=>Address(1),
107
            AD0=>Address(0), DO0=>Q(0));
108
 
109
end Structure;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.