Subversion Repositories single-14-segment-display-driver-w-decoder

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-- Entity: DisplayDriverWrapper

-- Date:2017-01-06  

-- Author: GL     

--

-- Description: 

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library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

--! @file

--! @brief Top wrapper for design FPGA prove.

--! @details This wrapper is designed for Lattice ECP5-5G Versa Development Kit.

entity DisplayDriverWrapper is

        port  (

        clk     : in std_logic;                                         --! input clock, xx MHz.

        n_rst   : in std_logic;                                         --! active low on board. active high in design.

        button  : in std_logic;                                         --! dev board tact switch to scroll through some test symbols, active low

        --! Typically the data fed to display (single or multiple) is provided for single display at a time.

        --! If multiple displays are required together with data goes display select (according typical dynamic display indication).

        disp_data : out std_logic_vector(14 downto 0);

        --! If more displays needs to be fed change disp_sel to vector with length equal to number of displays.

        --! Use principles of the standard dynamic indication: provide data then enable the displays sequentially.

        --! If brightness control is desired just AND the selector and the PWM controller output.

        disp_sel  : out std_logic

        );

        attribute syn_force_pad: boolean;

        attribute syn_force_pad of clk, n_rst, button, disp_sel, disp_data: signal is true;

end DisplayDriverWrapper;

--! @details The architecture consists of the DisplayDriverwDecoder_Top itself (as DUT) plus

--! sample symbol generator triggered by the button on the dev board

architecture arch of DisplayDriverWrapper is

    signal rst: std_logic;

    --! Debounce the glitches shorter than 4 clock cycles. Expand at will according the clock speed and glitch duration to filter.

    signal bttn_state_fifo: unsigned(3 downto 0);

    --! Active high i.e. '1' means "button pressed"

    signal bttn_state: std_logic;

    --! Incremented by 1 each time button is clicked. Provides ASCII symbol code for test purposes

    --! Counter range is double the decoder table size because codes from 0x00 to 0x7F are the symbols with decimal point dark.

    --! Codes from 0x80 to 0xFF are the same symbols but with decimal point lit. The decoder should handle this. The counter is lineary incremented.

    signal symbol_scan_cntr: unsigned(7 downto 0);

begin

--! invert n_rst to make it active high on design recommendation

rst <= not n_rst;

BtnDebouncer:process(clk)

begin

    if rising_edge(clk) then

        if rst = '1' then

            bttn_state_fifo <= (others=>'1');                           -- active low

            bttn_state <= '0';                                          -- active high

        else

            bttn_state_fifo <= shift_left(bttn_state_fifo,1);

            bttn_state_fifo(bttn_state_fifo'right) <= button;

            if bttn_state_fifo = "0000" then                            -- button actuated for more than X clocks and no bounces present

                bttn_state <= '1';                                      -- report button is actuated

            else

                bttn_state <= '0';

            end if;

        end if;

    end if;

end process;

AddrScanCntr:process(rst,bttn_state)

begin

    if rst='1' then

        symbol_scan_cntr <= (others=>'0');

    elsif rising_edge(bttn_state) then                                  -- TODO: Fix this to edge detector implementation

        symbol_scan_cntr <= symbol_scan_cntr + 1;                       -- I count ont the natural rolloff of this counter

    end if;

end process;

DDwD_Top:entity work.DisplayDriverwDecoder_Top

port map(

    clk         => clk,

    reset       => rst,

    ascii_in    => std_logic_vector(symbol_scan_cntr),

    wr_en       => '0',

    disp_data   => disp_data,

    disp_sel    => disp_sel

);

--disp_sel <= '1' when button = '1';

end arch;