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rpaley_yid |
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<meta name="GENERATOR" content="StarOffice/5.2 (Win32)">
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<meta name="AUTHOR" content="Robert Paley">
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<meta name="CREATED" content="20020728;14095738">
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<meta name="CHANGEDBY" content="Robert Paley">
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<meta name="CHANGED" content="20020728;15514460">
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<style>
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</style>
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</head>
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<body>
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<p align="right"><font size="3">B"H</font></p>
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<h1 style="text-align: center;"><font size="4" style="font-size: 16pt;">Description
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of single_port memory and test environment.</font></h1>
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<h2>Abstract: </h2>
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<p>A single port memory with testbench is described. The memory is
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implemented as three different architectures.</p>
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<h2>Port Interface:</h2>
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<table width="757" border="1" cellpadding="5" cellspacing="4">
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<col width="108"> <col width="118"> <col width="483"> <thead> <tr
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valign="top">
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<th width="108">
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<p>Port Name</p>
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</th>
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<th width="118">
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<p>Type</p>
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</th>
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<th width="483">
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<p>Description</p>
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</th>
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</tr>
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</thead> <tbody>
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<tr valign="top">
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<td width="108">
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<p>rnwtQ</p>
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</td>
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<td width="118">
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<p>Time</p>
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</td>
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<td width="483">
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<p>Time delay from rnw = read until data appears on q data bus.</p>
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</td>
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</tr>
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<tr valign="top">
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<td width="108">
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<p>d</p>
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</td>
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<td width="118">
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<p>data_inter_typ</p>
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</td>
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<td width="483">
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<p>Input data bus, type specified in single_port_pkg</p>
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</td>
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</tr>
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<tr valign="top">
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<td width="108">
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<p>q</p>
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</td>
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<td width="118">
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<p>data_inter_typ</p>
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</td>
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<td width="483">
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<p>Output data bus, type specified in single_port_pkg</p>
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</td>
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</tr>
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<tr valign="top">
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<td width="108">
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<p>a</p>
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</td>
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<td width="118">
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<p>addr_inter_typ</p>
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</td>
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<td width="483">
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<p>Address bus, type specified in single_port_pkg</p>
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</td>
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</tr>
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<tr valign="top">
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<td width="108">
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<p>rnw</p>
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</td>
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<td width="118">
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<p>STD_LOGIC</p>
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</td>
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<td width="483">
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<p>Read not write port</p>
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</td>
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</tr>
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<tr valign="top">
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<td width="108">
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<p>dealloc_mem</p>
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</td>
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<td width="118">
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<p>BOOLEAN</p>
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</td>
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<td width="483">
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<p>When set to true, deallocate linked list memory.</p>
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</td>
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</tr>
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</tbody>
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</table>
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<h2>Functional Description:</h2>
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<p>The single_port memory is implemented as three different
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architecures. The first architecture is called ArrayMemNoFlag, and
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implements the memory core as an array of STD_LOGIC_VECTOR. The memory
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is asynchronous and triggered on rnw'transaction. When rnw = '0', the
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data on bus "d" is loaded into the memory at the location specified by
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the addres bus "a". When rnw = '1', the data located in memory address
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"a" is loaded onto the output data bus "q". If a memory location is read
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which was not written to during the current simulation, 'U' are loaded
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onto the memory bus.</p>
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<p>The second architecture is called ArrayMem, and implements the
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memory core as an array of BIT_VECTOR. This arrangement allows less
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workstation memory to be used than the ArrayMemNoFlag architecture. The
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memory is asynchronous and triggered on rnw'transaction. When rnw = '0',
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the data on bus "d" is loaded into the memory at the location specified
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by the addres bus "a". When rnw = '1', the data located in memory
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address "a" is loaded onto the output data bus "q". If a memory location
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is read which was not written to during the current simulation, 'U' are
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loaded onto the memory bus.</p>
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<p>The third architecture is called LinkedList, and implements the
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memory core as a linked list of arrays of BIT_VECTOR. Each array in the
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linked list is a page of memory whose size is specified in
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single_port_pkg. This arrangement allows less workstation memory to be
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used than either the ArrayMemNoFlag or ArrayMem architectures. The
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memory is asynchronous and triggered on rnw'transaction. When rnw = '0',
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the data on bus "d" is loaded into the memory at the location specified
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by the addres bus "a". When rnw = '1', the data located in memory
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address "a" is loaded onto the output data bus "q". If a memory location
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is read which was not written to during the current simulation, 'U' are
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loaded onto the memory bus. To de-allocate the memory in the linked
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list, set dealloc_mem to true. </p>
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<h2>Functional Timing:</h2>
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<p>The single port memory is asynchronous and is triggered on
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rnw'transaction. When rnw is cleared to '0', the write occurs at the
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same time as rnw'transaction. When a read occurs, with rnw = '1' , data
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appears on the Q bus rnwtQ ns after rnw is set to '1'. The below sample
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timing diagram illustrates both a read and write operation.</p>
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<p><img src="../images/timing.jpg" name="Graphic1" align="left"
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width="958" height="251" border="0"><br clear="left">
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</p>
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<h2>Testbench Description:</h2>
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<p>The test bench is arranged as a client server architecture as
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specified by Bergeron<a class="sdfootnoteanc" name="sdfootnote1anc"
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href="#sdfootnote1sym"><sup>1</sup></a>. A diagram illustrating the
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testbench is given below.<br>
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<br>
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<img src="../images/tbschematic.jpg" name="Graphic2" align="left"
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width="838" height="371" border="0"><br clear="left">
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Two tests are specified in tc_single_port component. The first test
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writes data to two logical memory pages, and then reads them back
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verifying the correct data. The test case writes an error message to the
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console for every miscompare. The second case verifies that the
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single_port memory model outputs unknowns to the q bus if a read occurs
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for an unwritten memory location. Six configurations are specified in
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the test bench architecture tb_single_port, running both tests for each
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single_port architecture. <br>
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</p>
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<h2>Usage:</h2>
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<p>A Makefile is used to compile and run all of the tests in a Unix or
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like environment, such as Cygwin. The compilation and simulation is
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targetted to the SymphonyEDA tool available at <a
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href="www.symphonyeda.com">www.symphonyeda.com</a> .</p>
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<p>The source files and Makefile are located in {top}/VHDL<br>
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<br>
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To compile: make com</p>
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<p>To simulate all of the tests: make sim<br>
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</p>
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<p>To clean the compiled library: make clean</p>
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<p>The tests are labeled :</p>
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<ul>
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<li>ll_error</li>
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<li>ll_main</li>
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<li>mem_main<br>
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</li>
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<li>mem_error<br>
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</li>
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<li>memnoflag_main<br>
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</li>
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<li>memnoflag_error<br>
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</li>
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</ul>
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<p>To simulate any of these tests, type make {testname}</p>
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<p>Please contact Robert Paley at <a href="mailto:rpaley_yid@yahoo.com">rpaley_yid@opencores.org</a>
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if you have any questions or comments. </p>
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<div id="sdfootnote1">
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<p class="sdfootnote" style="margin-bottom: 0.2in;"><a
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class="sdfootnotesym" name="sdfootnote1sym" href="#sdfootnote1anc">1</a>Writing
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Testbenches , Functional Verification of HDL Testbenches. Chapter 6 –
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ISBN 0-7923-7766-4</p>
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</div>
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</body>
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</html>
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