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rpaley_yid |
#
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# Description: Top level make file for single_port test project.
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# make com to compile
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# make sim to simulate all tests
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# make ll_error to run this test only
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# make ll_main to run this test only
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# make mem_main to run this test only
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# make mem_error to run this test only
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# make memnoflag_main to run this test
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# make memnoflag_error to run this test
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# $Author: rpaley_yid $
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# $Date: 2003-01-14 21:48:11 $
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# $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/single_port/VHDL/Makefile,v 1.1.1.1 2003-01-14 21:48:11 rpaley_yid Exp $
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# $Locker: $
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# $Revision: 1.1.1.1 $
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# $State: Exp $
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# VCOM , VSIM , and WORK variables are set for Sonata simulator,
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# Change appropriately for your simulator. Ex.for Modeltech,
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# VCOM = vcom
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# VSIM = vsim
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# WORK = work
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SHELL = /bin/sh
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VCOM = vhdlp
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VCOMOPT = -s
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VSIM = vhdle
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VSIMOPT =
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WORK = work.sym
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## Need to figure out how to put Bourne shell stuff in Makefile
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## will do so to generate log files in
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## LOGDIR = ../LOG/
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## For now, log files are in VHDL directory.
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# List of main compiled objects, does not include configurations,
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# which are included in the tb_single_port.vhd file.
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# These targets are for the Sonata simulator, adjust accordingly for
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# your simulator.
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SINGLE_PORT_PKG_OBJ = $(WORK)/single_port_pkg/prim.var
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LINKED_LIST_MEM_OBJ = $(WORK)/linked_list_mem_pkg/prim.var
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PKG_IMAGE_OBJ = $(WORK)/pkg_image/prim.var
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SINGLE_PORT_OBJ = $(WORK)/single_port/prim.var
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TC_SINGLE_PORT_OBJ = $(WORK)/tc_single_port/prim.var
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TB_SINGLE_PORT_OBJ = $(WORK)/tb_single_port/prim.var
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LL_ERROR_DEP = $(WORK)/ll_error_cfg/prim.var
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LL_MAIN_DEP = $(WORK)/ll_main_cfg/prim.var
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MEM_MAIN_DEP = $(WORK)/mem_main_cfg/prim.var
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MEM_ERROR_DEP = $(WORK)/mem_error_cfg/prim.var
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MEMNOFLAG_MAIN_DEP = $(WORK)/memnoflag_main_cfg/prim.var
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MEMNOFLAG_ERROR_DEP = $(WORK)/memnoflag_error_cfg/prim.var
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LL_ERROR = $(LOGDIR)ll_error.log
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LL_MAIN = ll_main.log
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MEM_MAIN = mem_main.log
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MEM_ERROR = mem_error.log
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MEMNOFLAG_MAIN = memnoflag_main.log
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MEMNOFLAG_ERROR = memnoflag_error.log
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OBJS = $(SINGLE_PORT_PKG_OBJ) \
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$(LINKED_LIST_MEM_OBJ) \
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$(PKG_IMAGE_OBJ) \
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$(SINGLE_PORT_OBJ) \
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$(TC_SINGLE_PORT_OBJ) \
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$(TB_SINGLE_PORT_OBJ)
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SIMOBJS = $(LL_ERROR) \
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$(LL_MAIN) \
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$(MEM_MAIN) \
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$(MEM_ERROR) \
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$(MEMNOFLAG_MAIN) \
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$(MEMNOFLAG_ERROR)
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# Compile the project
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com: $(OBJS)
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# Clean the library
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clean:: $(WORK)
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# Simulate all tests
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sim: $(SIMOBJS)
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## Run only ll_error test
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ll_error: $(LL_ERROR)
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# Run onle ll_main test
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ll_main: $(LL_MAIN)
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# Run only mem_main test
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mem_main: $(MEM_MAIN)
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# Run only mem_error test
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mem_error: $(MEM_ERROR)
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# Run only memnoflag_main test
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memnoflag_main: $(MEMNOFLAG_MAIN)
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# Run only memnoflag_error test
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memnoflag_error: $(MEMNOFLAG_ERROR)
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# Target dependency rules to run tests
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$(LL_ERROR) : $(LL_ERROR_DEP)
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$(VSIM) $(VSIMOPT) ll_error_cfg | tee $@
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$(LL_MAIN) : $(LL_MAIN_DEP)
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$(VSIM) $(VSIMOPT) ll_main_cfg | tee $@
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$(MEM_MAIN) : $(MEM_MAIN_DEP)
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$(VSIM) $(VSIMOPT) mem_main_cfg | tee $@
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$(MEM_ERROR) : $(MEM_ERROR_DEP)
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$(VSIM) $(VSIMOPT) mem_error_cfg | tee $@
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$(MEMNOFLAG_MAIN) : $(MEMNOFLAG_MAIN_DEP)
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$(VSIM) $(VSIMOPT) memnoflag_main_cfg | tee $@
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$(MEMNOFLAG_ERROR) : $(MEMNOFLAG_ERROR_DEP)
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$(VSIM) $(VSIMOPT) memnoflag_error_cfg | tee $@
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# Target dependency rules to compile tests
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$(SINGLE_PORT_PKG_OBJ) : single_port_pkg.vhd
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$(VCOM) $(VCOMOPT) $<
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$(LINKED_LIST_MEM_OBJ) : linked_list_mem_pkg.vhd \
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$(SINGLE_PORT_PKG_OBJ)
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$(VCOM) $(VCOMOPT) $<
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$(PKG_IMAGE_OBJ) : pkg_image.vhd
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$(VCOM) $(VCOMOPT) $<
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$(SINGLE_PORT_OBJ) : single_port.vhd \
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$(SINGLE_PORT_PKG_OBJ) \
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$(LINKED_LIST_MEM_OBJ)
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$(VCOM) $(VCOMOPT) $<
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$(TC_SINGLE_PORT_OBJ) : tc_single_port.vhd \
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$(SINGLE_PORT_PKG_OBJ) \
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$(PKG_IMAGE_OBJ) \
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$(SINGLE_PORT_OBJ)
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$(VCOM) $(VCOMOPT) $<
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$(TB_SINGLE_PORT_OBJ) : tb_single_port.vhd \
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$(SINGLE_PORT_PKG_OBJ) \
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$(LINKED_LIST_MEM_OBJ) \
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$(SINGLE_PORT_OBJ) \
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$(TC_SINGLE_PORT_OBJ)
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$(VCOM) $(VCOMOPT) $<
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$(WORK) ::
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rm -rf $(WORK)/*
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####################################################################
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# $Log: not supported by cvs2svn $
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# Revision 1.1 2002/12/31 19:21:59 Default
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# Initial revision
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#
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#
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