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mgeng |
----------------------------------------------------------------------
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---- ----
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---- Single port asynchronous RAM simulation model ----
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---- ----
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---- This file is part of the single_port project ----
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---- ----
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---- Description ----
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---- Package file for single_port memory and testbench ----
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---- ----
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---- Authors: ----
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---- - Robert Paley, rpaley_yid@yahoo.com ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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---- References: ----
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---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
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---- ISBN: 1-55860-270-4 (pbk.) ----
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---- 2. Writing Testbenches - Functional Verification of HDL ----
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---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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2 |
rpaley_yid |
--
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6 |
mgeng |
-- CVS Revision History
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2 |
rpaley_yid |
--
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-- $Log: not supported by cvs2svn $
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mgeng |
-- Revision 1.3 2005/10/25 18:26:52 mgeng
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-- PAGENUM constant removed because the address bus width provides this information
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--
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mgeng |
-- Revision 1.2 2005/10/12 19:39:27 mgeng
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-- Buses unconstrained, LGPL header added
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--
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mgeng |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
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-- initial checkin
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--
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rpaley_yid |
-- Revision 1.1 2003/01/14 17:48:44 Default
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-- Initial revision
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--
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-- Revision 1.1 2002/12/24 17:58:49 Default
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-- Initial revision
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--
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mgeng |
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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rpaley_yid |
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mgeng |
PACKAGE single_port_pkg IS
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-- Address bus type for internal memory
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SUBTYPE addr_typ IS NATURAL;
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-- Operations testbench can do.
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TYPE do_typ IS ( init , read , write , dealloc , end_test );
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2 |
rpaley_yid |
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mgeng |
TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench
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do : do_typ;
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addr : INTEGER;
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data : INTEGER;
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event : BOOLEAN;
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mgeng |
END RECORD to_srv_typ;
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END PACKAGE single_port_pkg;
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rpaley_yid |
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mgeng |
PACKAGE BODY single_port_pkg IS
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END PACKAGE BODY single_port_pkg;
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