| 1 |
6 |
mgeng |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- Single port asynchronous RAM simulation model ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the single_port project ----
|
| 6 |
|
|
---- ----
|
| 7 |
|
|
---- Description ----
|
| 8 |
|
|
---- Package file for single_port memory and testbench ----
|
| 9 |
|
|
---- ----
|
| 10 |
|
|
---- Authors: ----
|
| 11 |
|
|
---- - Robert Paley, rpaley_yid@yahoo.com ----
|
| 12 |
|
|
---- - Michael Geng, vhdl@MichaelGeng.de ----
|
| 13 |
|
|
---- ----
|
| 14 |
|
|
---- References: ----
|
| 15 |
|
|
---- 1. The Designer's Guide to VHDL by Peter Ashenden ----
|
| 16 |
|
|
---- ISBN: 1-55860-270-4 (pbk.) ----
|
| 17 |
|
|
---- 2. Writing Testbenches - Functional Verification of HDL ----
|
| 18 |
|
|
---- models by Janick Bergeron | ISBN: 0-7923-7766-4 ----
|
| 19 |
|
|
---- ----
|
| 20 |
|
|
----------------------------------------------------------------------
|
| 21 |
|
|
---- ----
|
| 22 |
|
|
---- Copyright (C) 2005 Authors and OPENCORES.ORG ----
|
| 23 |
|
|
---- ----
|
| 24 |
|
|
---- This source file may be used and distributed without ----
|
| 25 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 26 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 27 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 28 |
|
|
---- ----
|
| 29 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 30 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 31 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 32 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 33 |
|
|
---- later version. ----
|
| 34 |
|
|
---- ----
|
| 35 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 36 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 37 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 38 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 39 |
|
|
---- details. ----
|
| 40 |
|
|
---- ----
|
| 41 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 42 |
|
|
---- Public License along with this source; if not, download it ----
|
| 43 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 44 |
|
|
---- ----
|
| 45 |
|
|
----------------------------------------------------------------------
|
| 46 |
2 |
rpaley_yid |
--
|
| 47 |
6 |
mgeng |
-- CVS Revision History
|
| 48 |
2 |
rpaley_yid |
--
|
| 49 |
|
|
-- $Log: not supported by cvs2svn $
|
| 50 |
7 |
mgeng |
-- Revision 1.2 2005/10/12 19:39:27 mgeng
|
| 51 |
|
|
-- Buses unconstrained, LGPL header added
|
| 52 |
|
|
--
|
| 53 |
6 |
mgeng |
-- Revision 1.1.1.1 2003/01/14 21:48:11 rpaley_yid
|
| 54 |
|
|
-- initial checkin
|
| 55 |
|
|
--
|
| 56 |
2 |
rpaley_yid |
-- Revision 1.1 2003/01/14 17:48:44 Default
|
| 57 |
|
|
-- Initial revision
|
| 58 |
|
|
--
|
| 59 |
|
|
-- Revision 1.1 2002/12/24 17:58:49 Default
|
| 60 |
|
|
-- Initial revision
|
| 61 |
|
|
--
|
| 62 |
6 |
mgeng |
LIBRARY IEEE;
|
| 63 |
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
| 64 |
|
|
USE IEEE.NUMERIC_STD.ALL;
|
| 65 |
2 |
rpaley_yid |
|
| 66 |
6 |
mgeng |
PACKAGE single_port_pkg IS
|
| 67 |
|
|
CONSTANT PAGEDEPTH : INTEGER := 256; -- memory page depth
|
| 68 |
|
|
-- Address bus type for internal memory
|
| 69 |
|
|
SUBTYPE addr_typ IS NATURAL;
|
| 70 |
|
|
-- Operations testbench can do.
|
| 71 |
|
|
TYPE do_typ IS ( init , read , write , dealloc , end_test );
|
| 72 |
2 |
rpaley_yid |
|
| 73 |
6 |
mgeng |
TYPE to_srv_typ IS RECORD -- Record passed from test case to test bench
|
| 74 |
|
|
do : do_typ;
|
| 75 |
|
|
addr : INTEGER;
|
| 76 |
|
|
data : INTEGER;
|
| 77 |
|
|
event : BOOLEAN;
|
| 78 |
|
|
END RECORD to_srv_typ;
|
| 79 |
|
|
END PACKAGE single_port_pkg;
|
| 80 |
2 |
rpaley_yid |
|
| 81 |
6 |
mgeng |
PACKAGE BODY single_port_pkg IS
|
| 82 |
|
|
END PACKAGE BODY single_port_pkg;
|
