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-- -----------------------------------------------------------------------------
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-- This file is a top level application for conencting the wb_lpc to the sio_logic
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-- written by : Istvan Nagy 11.01, 2019
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--
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-- A replacement for a chip like the Microchip SCH3227.
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-- The LPC IP has a 32bit wishbone bus, but only lower 8bits used for SIO access, with 8bit LPC cycles.
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-- Files from other projects needed:
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-- - UART below this module: https://opencores.org/projects/uart16550
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-- For the UART, use the 33MHz compliant version regs file: uart_regs_33m.v
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-- In uart_defines.v uncomment the "`define DATA_BUS_WIDTH_8"
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-- - PS2 below this module: http://www.opencores.org/projects/ps2/
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-- In the ps2_defines, uncomment `define PS2_AUX to enble the keyboard
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-- - LPC slave: https://opencores.org/projects/wb_lpc
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-- Use these files: wb_lpc_periph.v, wb_lpc_defines.v, serirq_defines.v, serirq_slave.v
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-- Some of the files had references, that needs rewriting to remove relative path: `include "wb_lpc_defines.v"
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-- In wb_lpc_periph.v change a line: always @(posedge clk_i or negedge nrst_i) ===> always @(posedge clk_i)
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-- - Write your own device-top level file, instantiating/connecting the LPC and SIO.
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-- Address range:
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-- - COM1: 3F8-3FFh
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-- - COM2: 2F8-2FFh
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-- - COM3: 3E8-3EFh
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-- - COM4: 2E8-2EFh
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-- - PS2: 60h AND 64h
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-- - post-code: 80h AND 81h
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-- - Custom board logic registers: 200h...207h (r/w regs connect in/out outside, ro regs out NC)
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-- -----------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--entity header ----------------------------------------------------------------
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entity example_sio_top is
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Port (
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clk_lpc : in std_logic;
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reset_n : in std_logic;
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lframe : in std_logic;
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lad : inout std_logic_vector(3 downto 0);
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serirq : inout std_logic;
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parallel_irq : IN std_logic_vector(31 downto 0);
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register_0_out : out std_logic_vector(7 downto 0);
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register_0_in : in std_logic_vector(7 downto 0);
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register_1_out : out std_logic_vector(7 downto 0);
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register_1_in : in std_logic_vector(7 downto 0);
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register_2_out : out std_logic_vector(7 downto 0);
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register_2_in : in std_logic_vector(7 downto 0);
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register_3_out : out std_logic_vector(7 downto 0);
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register_3_in : in std_logic_vector(7 downto 0);
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register_4_out : out std_logic_vector(7 downto 0);
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register_4_in : in std_logic_vector(7 downto 0);
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register_5_out : out std_logic_vector(7 downto 0);
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register_5_in : in std_logic_vector(7 downto 0);
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register_6_out : out std_logic_vector(7 downto 0);
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register_6_in : in std_logic_vector(7 downto 0);
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register_7_out : out std_logic_vector(7 downto 0);
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register_7_in : in std_logic_vector(7 downto 0);
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port80 : out std_logic_vector(7 downto 0);
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port81 : out std_logic_vector(7 downto 0);
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serial1_tx: out std_logic; serial1_rx: in std_logic; serial1_rts: out std_logic; serial1_cts: in std_logic; serial1_dtr: out std_logic; serial1_dsr: in std_logic; serial1_ri: in std_logic; serial1_dcd: in std_logic;
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serial2_tx: out std_logic; serial2_rx: in std_logic; serial2_rts: out std_logic; serial2_cts: in std_logic; serial2_dtr: out std_logic; serial2_dsr: in std_logic; serial2_ri: in std_logic; serial2_dcd: in std_logic;
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serial3_tx: out std_logic; serial3_rx: in std_logic; serial3_rts: out std_logic; serial3_cts: in std_logic; serial3_dtr: out std_logic; serial3_dsr: in std_logic; serial3_ri: in std_logic; serial3_dcd: in std_logic;
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serial4_tx: out std_logic; serial4_rx: in std_logic; serial4_rts: out std_logic; serial4_cts: in std_logic; serial4_dtr: out std_logic; serial4_dsr: in std_logic; serial4_ri: in std_logic; serial4_dcd: in std_logic;
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ps2_kbd_clk_pad_oe_o: out std_logic; ps2_kbd_clk_pad_o: out std_logic; ps2_kbd_data_pad_oe_o: out std_logic; ps2_kbd_data_pad_o: out std_logic;
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ps2_aux_clk_pad_oe_o: out std_logic; ps2_aux_clk_pad_o: out std_logic; ps2_aux_data_pad_oe_o: out std_logic; ps2_aux_data_pad_o: out std_logic;
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ps2_kbd_clk_pad_i: in std_logic; ps2_kbd_data_pad_i: in std_logic; ps2_aux_clk_pad_i : in std_logic; ps2_aux_data_pad_i: in std_logic; kb_rstout: out std_logic
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);
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end example_sio_top;
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--architecture start ------------------------------------------------------------
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architecture Behavioral of example_sio_top is
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-- INTERNAL SIGNALS -------------------------------------------------------------
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SIGNAL dummy0: std_logic;
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SIGNAL dummy1: std_logic_VECTOR(6 DOWNTO 0);
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SIGNAL xwbm_adr_i : std_logic_vector(31 downto 0);
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SIGNAL xwbm_dat_i : std_logic_vector(31 downto 0);
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SIGNAL xwbm_sel_i : std_logic_vector(3 downto 0);
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SIGNAL xwbm_tga_i : std_logic_vector(1 downto 0);
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SIGNAL xwbm_we_i : std_logic;
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SIGNAL xwbm_stb_i : std_logic;
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SIGNAL xwbm_cyc_i : std_logic;
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SIGNAL xwbm_dat_o : std_logic_vector(31 downto 0);
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SIGNAL xwbm_ack_o : std_logic;
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SIGNAL xwbm_err_o : std_logic;
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SIGNAL dma_bs1 : std_logic_vector(2 downto 0);
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SIGNAL dma_bs2 : std_logic;
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SIGNAL serirq_i : std_logic;
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SIGNAL serirq_o : std_logic;
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SIGNAL serirq_oe : std_logic;
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SIGNAL lad_i : std_logic_vector(3 downto 0);
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SIGNAL lad_o : std_logic_vector(3 downto 0);
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SIGNAL lad_oe : std_logic;
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--------- COMPONENT DECLARATIONS (introducing the IPs) --------------------------
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COMPONENT sio_logic
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PORT(
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clk : IN std_logic;
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reset_n : IN std_logic;
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wbm_adr_i : IN std_logic_vector(31 downto 0);
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wbm_dat_i : IN std_logic_vector(31 downto 0);
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wbm_sel_i : IN std_logic_vector(3 downto 0);
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wbm_tga_i : IN std_logic_vector(1 downto 0);
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wbm_we_i : IN std_logic;
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wbm_stb_i : IN std_logic;
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wbm_cyc_i : IN std_logic;
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register_0_in : IN std_logic_vector(7 downto 0);
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register_1_in : IN std_logic_vector(7 downto 0);
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register_2_in : IN std_logic_vector(7 downto 0);
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register_3_in : IN std_logic_vector(7 downto 0);
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register_4_in : IN std_logic_vector(7 downto 0);
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register_5_in : IN std_logic_vector(7 downto 0);
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register_6_in : IN std_logic_vector(7 downto 0);
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register_7_in : IN std_logic_vector(7 downto 0);
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serial1_rx : IN std_logic;
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serial1_cts : IN std_logic;
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serial1_dsr : IN std_logic;
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serial1_ri : IN std_logic;
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serial1_dcd : IN std_logic;
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serial2_rx : IN std_logic;
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serial2_cts : IN std_logic;
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serial2_dsr : IN std_logic;
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serial2_ri : IN std_logic;
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serial2_dcd : IN std_logic;
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serial3_rx : IN std_logic;
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serial3_cts : IN std_logic;
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serial3_dsr : IN std_logic;
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serial3_ri : IN std_logic;
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serial3_dcd : IN std_logic;
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serial4_rx : IN std_logic;
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serial4_cts : IN std_logic;
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serial4_dsr : IN std_logic;
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serial4_ri : IN std_logic;
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serial4_dcd : IN std_logic;
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ps2_kbd_clk_pad_i : IN std_logic;
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ps2_kbd_data_pad_i : IN std_logic;
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ps2_aux_clk_pad_i : IN std_logic;
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ps2_aux_data_pad_i : IN std_logic;
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wbm_dat_o : OUT std_logic_vector(31 downto 0);
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wbm_ack_o : OUT std_logic;
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wbm_err_o : OUT std_logic;
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register_0_out : OUT std_logic_vector(7 downto 0);
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register_1_out : OUT std_logic_vector(7 downto 0);
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register_2_out : OUT std_logic_vector(7 downto 0);
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register_3_out : OUT std_logic_vector(7 downto 0);
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register_4_out : OUT std_logic_vector(7 downto 0);
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register_5_out : OUT std_logic_vector(7 downto 0);
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register_6_out : OUT std_logic_vector(7 downto 0);
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register_7_out : OUT std_logic_vector(7 downto 0);
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port80 : OUT std_logic_vector(7 downto 0);
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port81 : OUT std_logic_vector(7 downto 0);
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serial1_tx : OUT std_logic;
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serial1_rts : OUT std_logic;
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serial1_dtr : OUT std_logic;
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serial2_tx : OUT std_logic;
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serial2_rts : OUT std_logic;
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serial2_dtr : OUT std_logic;
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serial3_tx : OUT std_logic;
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serial3_rts : OUT std_logic;
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serial3_dtr : OUT std_logic;
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serial4_tx : OUT std_logic;
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serial4_rts : OUT std_logic;
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serial4_dtr : OUT std_logic;
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--kb_rstout : OUT std_logic;
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ps2_kbd_clk_pad_oe_o : OUT std_logic;
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ps2_kbd_clk_pad_o : OUT std_logic;
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ps2_kbd_data_pad_oe_o : OUT std_logic;
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ps2_kbd_data_pad_o : OUT std_logic;
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ps2_aux_clk_pad_oe_o : OUT std_logic;
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ps2_aux_clk_pad_o : OUT std_logic;
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ps2_aux_data_pad_oe_o : OUT std_logic;
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ps2_aux_data_pad_o : OUT std_logic
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);
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END COMPONENT;
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COMPONENT wb_lpc_periph
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PORT(
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clk_i : IN std_logic;
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nrst_i : IN std_logic;
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wbm_dat_i : IN std_logic_vector(31 downto 0);
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wbm_ack_i : IN std_logic;
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wbm_err_i : IN std_logic;
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lframe_i : IN std_logic;
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lad_i : IN std_logic_vector(3 downto 0);
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wbm_adr_o : OUT std_logic_vector(31 downto 0);
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wbm_dat_o : OUT std_logic_vector(31 downto 0);
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wbm_sel_o : OUT std_logic_vector(3 downto 0);
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wbm_tga_o : OUT std_logic_vector(1 downto 0);
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wbm_we_o : OUT std_logic;
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wbm_stb_o : OUT std_logic;
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wbm_cyc_o : OUT std_logic;
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dma_chan_o : OUT std_logic_vector(2 downto 0);
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dma_tc_o : OUT std_logic;
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lad_o : OUT std_logic_vector(3 downto 0);
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lad_oe : OUT std_logic
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);
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END COMPONENT;
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COMPONENT serirq_slave
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PORT(
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clk_i : IN std_logic;
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nrst_i : IN std_logic;
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irq_i : IN std_logic_vector(31 downto 0);
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serirq_i : IN std_logic;
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serirq_o : OUT std_logic;
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serirq_oe : OUT std_logic
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);
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END COMPONENT;
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--architecture body start -------------------------------------------------------
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begin
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--------- COMPONENT INSTALLATIONS (connecting the IPs to local signals) ---------
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Inst_sio_logic: sio_logic PORT MAP(
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clk => clk_lpc ,
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reset_n => reset_n ,
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wbm_adr_i => xwbm_adr_i,
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wbm_dat_i => xwbm_dat_i,
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wbm_dat_o => xwbm_dat_o,
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wbm_sel_i => xwbm_sel_i,
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wbm_tga_i => xwbm_tga_i,
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wbm_we_i => xwbm_we_i,
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wbm_stb_i => xwbm_stb_i,
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wbm_cyc_i => xwbm_cyc_i,
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wbm_ack_o => xwbm_ack_o,
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wbm_err_o => xwbm_err_o,
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register_0_out => register_0_out,
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register_0_in => register_0_in,
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register_1_out => register_1_out,
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register_1_in => register_1_in,
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register_2_out => register_2_out,
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register_2_in => register_2_in,
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register_3_out => register_3_out,
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register_3_in => register_3_in,
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register_4_out => register_4_out,
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register_4_in => register_4_in,
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register_5_out => register_5_out,
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register_5_in => register_5_in,
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register_6_out => register_6_out,
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register_6_in => register_6_in,
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register_7_out => register_7_out,
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register_7_in => register_7_in,
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port80 => port80,
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port81 => port81,
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serial1_tx => serial1_tx,
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serial1_rx => serial1_rx,
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serial1_rts => serial1_rts,
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serial1_cts => serial1_cts,
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serial1_dtr => serial1_dtr,
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serial1_dsr => serial1_dsr,
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serial1_ri => serial1_ri,
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serial1_dcd => serial1_dcd,
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serial2_tx => serial2_tx,
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serial2_rx => serial2_rx,
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serial2_rts => serial2_rts,
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serial2_cts => serial2_cts,
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serial2_dtr => serial2_dtr,
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serial2_dsr => serial2_dsr,
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serial2_ri => serial2_ri,
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serial2_dcd => serial2_dcd,
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serial3_tx => serial3_tx,
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serial3_rx => serial3_rx,
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serial3_rts => serial3_rts,
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serial3_cts => serial3_cts,
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serial3_dtr => serial3_dtr,
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serial3_dsr => serial3_dsr,
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serial3_ri => serial3_ri,
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serial3_dcd => serial3_dcd,
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serial4_tx => serial4_tx,
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serial4_rx => serial4_rx,
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serial4_rts => serial4_rts,
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serial4_cts => serial4_cts,
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serial4_dtr => serial4_dtr,
|
283 |
|
|
serial4_dsr => serial4_dsr,
|
284 |
|
|
serial4_ri => serial4_ri,
|
285 |
|
|
serial4_dcd => serial4_dcd,
|
286 |
|
|
--kb_rstout => kb_rstout, --missing???
|
287 |
|
|
ps2_kbd_clk_pad_oe_o => ps2_kbd_clk_pad_oe_o,
|
288 |
|
|
ps2_kbd_clk_pad_o => ps2_kbd_clk_pad_o,
|
289 |
|
|
ps2_kbd_data_pad_oe_o => ps2_kbd_data_pad_oe_o,
|
290 |
|
|
ps2_kbd_data_pad_o => ps2_kbd_data_pad_o,
|
291 |
|
|
ps2_aux_clk_pad_oe_o => ps2_aux_clk_pad_oe_o,
|
292 |
|
|
ps2_aux_clk_pad_o => ps2_aux_clk_pad_o,
|
293 |
|
|
ps2_aux_data_pad_oe_o => ps2_aux_data_pad_oe_o,
|
294 |
|
|
ps2_aux_data_pad_o => ps2_aux_data_pad_o,
|
295 |
|
|
ps2_kbd_clk_pad_i => ps2_kbd_clk_pad_i,
|
296 |
|
|
ps2_kbd_data_pad_i => ps2_kbd_data_pad_i,
|
297 |
|
|
ps2_aux_clk_pad_i => ps2_aux_clk_pad_i,
|
298 |
|
|
ps2_aux_data_pad_i => ps2_aux_data_pad_i
|
299 |
|
|
|
300 |
|
|
|
301 |
|
|
);
|
302 |
|
|
|
303 |
|
|
|
304 |
|
|
Inst_wb_lpc_periph: wb_lpc_periph PORT MAP(
|
305 |
|
|
clk_i => clk_lpc ,
|
306 |
|
|
nrst_i => reset_n ,
|
307 |
|
|
wbm_adr_o => xwbm_adr_i ,
|
308 |
|
|
wbm_dat_o => xwbm_dat_i ,
|
309 |
|
|
wbm_dat_i => xwbm_dat_o ,
|
310 |
|
|
wbm_sel_o => xwbm_sel_i ,
|
311 |
|
|
wbm_tga_o => xwbm_tga_i ,
|
312 |
|
|
wbm_we_o => xwbm_we_i ,
|
313 |
|
|
wbm_stb_o => xwbm_stb_i ,
|
314 |
|
|
wbm_cyc_o => xwbm_cyc_i ,
|
315 |
|
|
wbm_ack_i => xwbm_ack_o ,
|
316 |
|
|
wbm_err_i => xwbm_err_o ,
|
317 |
|
|
dma_chan_o => dma_bs1,
|
318 |
|
|
dma_tc_o => dma_bs2,
|
319 |
|
|
lframe_i => lframe ,
|
320 |
|
|
lad_i => lad_i,
|
321 |
|
|
lad_o => lad_o ,
|
322 |
|
|
lad_oe => lad_oe
|
323 |
|
|
);
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
Inst_serirq_slave: serirq_slave PORT MAP(
|
327 |
|
|
clk_i => clk_lpc ,
|
328 |
|
|
nrst_i => reset_n ,
|
329 |
|
|
irq_i => parallel_irq ,
|
330 |
|
|
serirq_o => serirq_o ,
|
331 |
|
|
serirq_i => serirq_i ,
|
332 |
|
|
serirq_oe => serirq_oe
|
333 |
|
|
);
|
334 |
|
|
|
335 |
|
|
|
336 |
|
|
|
337 |
|
|
|
338 |
|
|
-- local Logic ------------------------------------------------------------------
|
339 |
|
|
|
340 |
|
|
process ( reset_n, lad_oe, lad_o)
|
341 |
|
|
begin
|
342 |
|
|
if (reset_n='0') then
|
343 |
|
|
lad <= "ZZZZ";
|
344 |
|
|
else
|
345 |
|
|
if (lad_oe='1') then lad <= lad_o;
|
346 |
|
|
else lad <= "ZZZZ";
|
347 |
|
|
end if;
|
348 |
|
|
end if;
|
349 |
|
|
end process;
|
350 |
|
|
lad_i <= lad;
|
351 |
|
|
|
352 |
|
|
process ( reset_n, serirq_oe , serirq_o )
|
353 |
|
|
begin
|
354 |
|
|
if (reset_n='0') then
|
355 |
|
|
serirq <= 'Z';
|
356 |
|
|
else
|
357 |
|
|
if (serirq_oe ='1') then serirq <= serirq_o ;
|
358 |
|
|
else serirq <= 'Z';
|
359 |
|
|
end if;
|
360 |
|
|
end if;
|
361 |
|
|
end process;
|
362 |
|
|
serirq_i <= serirq;
|
363 |
|
|
|
364 |
|
|
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
--end file ----------------------------------------------------------------------
|
369 |
|
|
end Behavioral;
|