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[/] [smbus_controller/] [trunk/] [hw/] [simulations/] [Testbench_SMBusController_behav.wcfg] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ldalmasso
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      clock_12M
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      clock_12M
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      reset
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      reset
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      start
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      start
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      mode[1:0]
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      mode[1:0]
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      slave_addr[6:0]
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      slave_addr[6:0]
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      cmd_enable
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      cmd_enable
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      pec_enable
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      pec_enable
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      cmd[7:0]
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      cmd[7:0]
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      state
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      state
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      clock_divider
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      clock_divider
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      clock_enable
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      clock_enable
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      clock_enable_1_4
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      clock_enable_1_4
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      clock_enable_3_4
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      clock_enable_3_4
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      bit_counter[3:0]
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      bit_counter[3:0]
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      bit_counter_end
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      bit_counter_end
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      byte_counter
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      byte_counter
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      byte_counter_end
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      byte_counter_end
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      smbclk
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      smbclk
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      smbdat
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      smbdat
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      smbdat_out
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      smbdat_out
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      smbdat_out_reg[7:0]
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      smbdat_out_reg[7:0]
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      BINARYRADIX
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      smbdat_in_reg[7:0]
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      smbdat_in_reg[7:0]
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      data_read[7:0]
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      data_read[7:0]
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      HEXRADIX
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      data_read_valid
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      data_read_valid
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      smbus_pec_reset
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      smbus_pec_reset
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      smbus_pec_enable
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      smbus_pec_enable
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      smbus_pec_input[7:0]
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      smbus_pec_input[7:0]
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      smbus_pec_value[7:0]
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      smbus_pec_value[7:0]
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      smbus_pec_received[7:0]
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      smbus_pec_received[7:0]
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      smbus_busy
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      smbus_busy
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      smbus_timeout
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      smbus_timeout
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      smbus_arbitration
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      smbus_arbitration
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      smbclk_stretching
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      smbclk_stretching
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      ready
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      ready
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      error
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      error
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      busy
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      busy
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