URL https://opencores.org/ocsvn/smii/smii/trunk

Subversion Repositories smii

[/] [smii/] [trunk/] [rtl/] [verilog/] [smii.v] - Blame information for rev 4

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  SMII                                                        ////
////                                                              ////
////  Description                                                 ////
////  Low pin count serial MII ethernet interface                 ////
////                                                              ////
////  To Do:                                                      ////
////   -                                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Michael Unneback, unneback@opencores.org              ////
////        ORSoC AB          michael.unneback@orsoc.se           ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
module obufdff
  (
   input d,
   output reg pad,
   input clk,
   input rst
   );
   always @ (posedge clk or posedge rst)
     if (rst)
       pad <= #1 1'b0;
     else
       pad <= #1 d;
endmodule
module ibufdff
  (
   input pad,
   output reg q,
   input clk,
   input rst
   );
   always @ (posedge clk or posedge rst)
     if (rst)
       q <= #1 1'b0;
     else
       q <= #1 pad;
endmodule
module iobuftri
  (
   input i,
   input oe,
   output o,
   inout pad
   );
   assign #1 pad = oe ? i : 1'bz;
   assign #1 i = pad;
endmodule
module obuf
  (
   input i,
   inout pad
   );
   assign #1 pad = i;
endmodule
module smii_sync
  (
    output            sync,
    output reg [1:10] state,
    input             clk,
    input             rst
   );
   always @ (posedge clk or posedge rst)
     if (rst)
       state <= 10'b0000000001;
     else
       state <= {state[10],state[1:9]};
   assign sync = state[1];
endmodule
module smii_txrx
  (
    output     tx,
    input      rx,
    input [3:0] mtxd,
    input       mtxen,
    input       mtxerr,
    output      mtx_clk,
    output reg [3:0] mrxd,
    output reg   mrxdv,
    output reg   mrxerr,
    output       mrx_clk,
    output       mcoll,
    output reg   mcrs,
    input [1:10] state,
    input        clk,
    input        rst
   );
   reg [0:7]              tx_data_reg;
   reg                   tx_data_reg_valid;
   reg                   a0;
   reg                   state_data;
   reg [3:0]      rx_tmp;
   reg           speed;
   reg           duplex;
   reg           link;
   reg           jabber;
   reg           mtx_clk_tmp, mrx_clk_tmp;
   reg [3:0]      tx_cnt;
   reg [3:0]      rx_cnt;
   always @ (posedge clk or posedge rst)
     if (rst)
       tx_cnt <= 4'd0;
     else
       if (speed)
         tx_cnt <= 4'd0;
       else if (state[10])
         if (tx_cnt == 4'd9)
           tx_cnt <= 4'd0;
         else
           tx_cnt <= tx_cnt + 4'd1;
     always @ (posedge clk or posedge rst)
     if (rst)
       mtx_clk_tmp <= 1'b0;
     else
       if ((state[10] | state[5]) & (tx_cnt == 4'd0))
         mtx_clk_tmp <= 1'b1;
       else if (state[2] | state[7])
         mtx_clk_tmp <= 1'b0;
   assign #1 mtx_clk = mtx_clk_tmp;
   always @ (posedge clk or posedge rst)
     if (rst)
       begin
          tx_data_reg <= 8'd0;
          tx_data_reg_valid <= 1'b0;
          a0 <= 1'b0;
       end
     else
       if ((state[4] | state[9]) & (tx_cnt == 4'd0))
         begin
            if (!mtxen)
              a0 <= 1'b0;
            else
              a0 <= ~a0;
            if (!mtxen & !a0)
              tx_data_reg_valid <= 1'b0;
            else if (a0)
              tx_data_reg_valid <= 1'b1;
            if (mtxen & !a0)
              tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
            else if (mtxen & a0)
              tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
         end
   always @ (posedge clk or posedge rst)
     if (rst)
       state_data <= 1'b0;
     else
       if (state[1] & (tx_cnt == 4'd0))
         state_data <= tx_data_reg_valid;
   assign tx = state[1] ? mtxerr :
               state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
               state_data ? |(state[2:10] & tx_data_reg) :
               |(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});
   always @ (posedge clk or posedge rst)
     if (rst)
       rx_cnt <= 4'd0;
     else
       if (speed)
         rx_cnt <= 4'd0;
       else if (!mrxdv & state[8] & rx_tmp[3])
         rx_cnt <= 4'd9;
       else if (state[10])
         if (rx_cnt == 4'd9)
           rx_cnt <= 4'd0;
         else
           rx_cnt <= rx_cnt + 4'd1;
   always @ (posedge clk or posedge rst)
     if (rst)
       begin
          {mcrs, mrxdv, mrxerr, speed, duplex, link, jabber} <= 7'b0001110;
          rx_tmp <= 4'h0;
          mrxd <= 4'h0;
       end
     else
       begin
          rx_tmp[2:0] <= {rx,rx_tmp[2:1]};
          if (state[3])
            mcrs <= rx;
          if (state[4])
            rx_tmp[3] <= rx;
          if (rx_tmp[3])
            begin
               if (state[8])
                 {mrxdv,mrxd} <= #1 {rx_tmp[3],rx,rx_tmp[2:0]};
               else if (state[2])
                 mrxd <= #1 {rx,rx_tmp[2:0]};
            end
          else
            begin
               if (state[5])
                 mrxerr <= #1 rx;
               if (state[6])
                 speed <= #1 rx;
               if (state[7])
                 duplex <= #1 rx;
               if (state[8])
                 begin
                    link <= #1 rx;
                    mrxdv <= #1 1'b0;
                 end
               if (state[9])
                 jabber <= #1 rx;
            end
       end
   always @ (posedge clk or posedge rst)
     if (rst)
       mrx_clk_tmp <= 1'b0;
     else
       if ((state[1] | state[6]) & (rx_cnt == 4'd0))
         mrx_clk_tmp <= 1'b1;
       else if (state[3] | state[8])
         mrx_clk_tmp <= 1'b0;
   assign #1 mrx_clk = mrx_clk_tmp;
   assign mcoll = mcrs & mtxen;
endmodule

Line No.	Rev	Author	Line
1	3	unneback	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// SMII ////`
4			`//// ////`
5			`//// Description ////`
6			`//// Low pin count serial MII ethernet interface ////`
7			`//// ////`
8			`//// To Do: ////`
9			`//// - ////`
10			`//// ////`
11			`//// Author(s): ////`
12			`//// - Michael Unneback, unneback@opencores.org ////`
13			`//// ORSoC AB michael.unneback@orsoc.se ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2009 Authors and OPENCORES.ORG ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41			`module obufdff`
42			`(`
43			`input d,`
44			`output reg pad,`
45			`input clk,`
46			`input rst`
47			`);`
48			`always @ (posedge clk or posedge rst)`
49			`if (rst)`
50			`pad <= #1 1'b0;`
51			`else`
52			`pad <= #1 d;`
53			`endmodule`
54			`module ibufdff`
55			`(`
56			`input pad,`
57			`output reg q,`
58			`input clk,`
59			`input rst`
60			`);`
61			`always @ (posedge clk or posedge rst)`
62			`if (rst)`
63			`q <= #1 1'b0;`
64			`else`
65			`q <= #1 pad;`
66			`endmodule`
67			`module iobuftri`
68			`(`
69			`input i,`
70			`input oe,`
71			`output o,`
72			`inout pad`
73			`);`
74			`assign #1 pad = oe ? i : 1'bz;`
75			`assign #1 i = pad;`
76			`endmodule`
77			`module obuf`
78			`(`
79			`input i,`
80			`inout pad`
81			`);`
82			`assign #1 pad = i;`
83			`endmodule`
84			`module smii_sync`
85			`(`
86			`output sync,`
87			`output reg [1:10] state,`
88			`input clk,`
89			`input rst`
90			`);`
91			`always @ (posedge clk or posedge rst)`
92			`if (rst)`
93			`state <= 10'b0000000001;`
94			`else`
95			`state <= {state[10],state[1:9]};`
96			`assign sync = state[1];`
97			`endmodule`
98			`module smii_txrx`
99			`(`
100			`output tx,`
101			`input rx,`
102			`input [3:0] mtxd,`
103			`input mtxen,`
104			`input mtxerr,`
105			`output mtx_clk,`
106			`output reg [3:0] mrxd,`
107			`output reg mrxdv,`
108			`output reg mrxerr,`
109			`output mrx_clk,`
110			`output mcoll,`
111			`output reg mcrs,`
112			`input [1:10] state,`
113			`input clk,`
114			`input rst`
115			`);`
116			`reg [0:7] tx_data_reg;`
117			`reg tx_data_reg_valid;`
118			`reg a0;`
119			`reg state_data;`
120			`reg [3:0] rx_tmp;`
121			`reg speed;`
122			`reg duplex;`
123			`reg link;`
124			`reg jabber;`
125			`reg mtx_clk_tmp, mrx_clk_tmp;`
126			`reg [3:0] tx_cnt;`
127			`reg [3:0] rx_cnt;`
128			`always @ (posedge clk or posedge rst)`
129			`if (rst)`
130			`tx_cnt <= 4'd0;`
131			`else`
132			`if (speed)`
133			`tx_cnt <= 4'd0;`
134			`else if (state[10])`
135			`if (tx_cnt == 4'd9)`
136			`tx_cnt <= 4'd0;`
137			`else`
138			`tx_cnt <= tx_cnt + 4'd1;`
139			`always @ (posedge clk or posedge rst)`
140			`if (rst)`
141			`mtx_clk_tmp <= 1'b0;`
142			`else`
143			`if ((state[10] \| state[5]) & (tx_cnt == 4'd0))`
144			`mtx_clk_tmp <= 1'b1;`
145			`else if (state[2] \| state[7])`
146			`mtx_clk_tmp <= 1'b0;`
147	4	unneback	`assign #1 mtx_clk = mtx_clk_tmp;`
148	3	unneback	`always @ (posedge clk or posedge rst)`
149			`if (rst)`
150			`begin`
151			`tx_data_reg <= 8'd0;`
152			`tx_data_reg_valid <= 1'b0;`
153			`a0 <= 1'b0;`
154			`end`
155			`else`
156			`if ((state[4] \| state[9]) & (tx_cnt == 4'd0))`
157			`begin`
158			`if (!mtxen)`
159			`a0 <= 1'b0;`
160			`else`
161			`a0 <= ~a0;`
162			`if (!mtxen & !a0)`
163			`tx_data_reg_valid <= 1'b0;`
164			`else if (a0)`
165			`tx_data_reg_valid <= 1'b1;`
166			`if (mtxen & !a0)`
167			`tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};`
168			`else if (mtxen & a0)`
169			`tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};`
170			`end`
171			`always @ (posedge clk or posedge rst)`
172			`if (rst)`
173			`state_data <= 1'b0;`
174			`else`
175			`if (state[1] & (tx_cnt == 4'd0))`
176			`state_data <= tx_data_reg_valid;`
177			`assign tx = state[1] ? mtxerr :`
178			`state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) \| state_data) :`
179			`state_data ? \|(state[2:10] & tx_data_reg) :`
180			`\|(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});`
181			`always @ (posedge clk or posedge rst)`
182			`if (rst)`
183			`rx_cnt <= 4'd0;`
184			`else`
185			`if (speed)`
186			`rx_cnt <= 4'd0;`
187			`else if (!mrxdv & state[8] & rx_tmp[3])`
188			`rx_cnt <= 4'd9;`
189			`else if (state[10])`
190			`if (rx_cnt == 4'd9)`
191			`rx_cnt <= 4'd0;`
192			`else`
193			`rx_cnt <= rx_cnt + 4'd1;`
194			`always @ (posedge clk or posedge rst)`
195			`if (rst)`
196			`begin`
197			`{mcrs, mrxdv, mrxerr, speed, duplex, link, jabber} <= 7'b0001110;`
198			`rx_tmp <= 4'h0;`
199			`mrxd <= 4'h0;`
200			`end`
201			`else`
202			`begin`
203			`rx_tmp[2:0] <= {rx,rx_tmp[2:1]};`
204			`if (state[3])`
205			`mcrs <= rx;`
206			`if (state[4])`
207			`rx_tmp[3] <= rx;`
208			`if (rx_tmp[3])`
209			`begin`
210			`if (state[8])`
211			`{mrxdv,mrxd} <= #1 {rx_tmp[3],rx,rx_tmp[2:0]};`
212			`else if (state[2])`
213			`mrxd <= #1 {rx,rx_tmp[2:0]};`
214			`end`
215			`else`
216			`begin`
217			`if (state[5])`
218			`mrxerr <= #1 rx;`
219			`if (state[6])`
220			`speed <= #1 rx;`
221			`if (state[7])`
222			`duplex <= #1 rx;`
223			`if (state[8])`
224			`begin`
225			`link <= #1 rx;`
226			`mrxdv <= #1 1'b0;`
227			`end`
228			`if (state[9])`
229			`jabber <= #1 rx;`
230			`end`
231			`end`
232			`always @ (posedge clk or posedge rst)`
233			`if (rst)`
234			`mrx_clk_tmp <= 1'b0;`
235			`else`
236			`if ((state[1] \| state[6]) & (rx_cnt == 4'd0))`
237			`mrx_clk_tmp <= 1'b1;`
238			`else if (state[3] \| state[8])`
239			`mrx_clk_tmp <= 1'b0;`
240	4	unneback	`assign #1 mrx_clk = mrx_clk_tmp;`
241	3	unneback	`assign mcoll = mcrs & mtxen;`
242			`endmodule`

Browse

Tools

Subversion Repositories smii

[/] [smii/] [trunk/] [rtl/] [verilog/] [smii.v] - Blame information for rev 4