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pozniak |
use std.textio.all;
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library ieee;
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use ieee.std_logic_1164.all;
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package vBUS is
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-- interface declaration
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type TvBUSnodeType is (INPUT, OUTPUT);
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type TvBUSnodeMode is (PART, PREG, WORD, WREG);
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type TvBUSnodeDesc is record
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name :string(1 to 32);
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dir :TvBUSnodeType;
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mode :TvBUSnodeMode;
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size :positive;
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end record;
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type TvBUSdesc is array (natural range <>) of TvBUSnodeDesc;
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function vBUSnodeDesc(name :string; dir :TvBUSnodeType; mode :TvBUSnodeMode; size: natural) return TvBUSnodeDesc;
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-- interface configuration
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type TvBUSnodeCfg is record
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name :string(TvBUSnodeDesc.name'range);
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dir :TvBUSnodeType;
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mode :TvBUSnodeMode;
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size :natural;
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addr :natural;
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vpos :natural;
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end record;
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type TvBUScfg is array (natural range <>) of TvBUSnodeCfg;
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impure function vBUScreator(asize, dsize :positive; desc :TvBUSdesc; fname :string) return TvBUScfg;
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function vBUSlength(cfg :TvBUScfg) return natural;
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-- nodes implementation
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function vBUSnodeWordSize (name :string; cfg :TvBUScfg) return natural;
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function vBUSnodeOutputData (name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector;
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function vBUSnodeOutputEnable(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector;
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function vBUSnodeInputData (name :string; cfg :TvBUScfg; vBUS, data :std_logic_vector) return std_logic_vector;
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function vBUSnodeInputEnable (name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector;
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-- local interface implementation
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component vBUSinterface is
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generic (
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vBUScfg :TvBUScfg);
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port(
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resetN :in std_logic;
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enableN :in std_logic;
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strobeN :in std_logic;
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readN :in std_logic;
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addr :in std_logic_vector;
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data_wr :in std_logic_vector;
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data_rd :out std_logic_vector;
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vbus :inout std_logic_vector);
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end component vBUSinterface;
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end package;
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package body vBUS is
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function \vBUSname\(name :string) return string is
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variable iname :string(1 to TvBUSnodeDesc.name'length);
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begin
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iname := (others => ' ');
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iname(1 to name'length) := name;
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return(iname);
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end function;
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function vBUSnodeDesc(name :string; dir :TvBUSnodeType; mode :TvBUSnodeMode; size: natural) return TvBUSnodeDesc is
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variable item :TvBUSnodeDesc;
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begin
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item.name := \vBUSname\(name);
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item.dir := dir;
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item.mode := mode;
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item.size := size;
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return(item);
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end function;
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impure function vBUScreator(asize, dsize :positive; desc :TvBUSdesc; fname :string) return TvBUScfg is
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variable vBUS :TvBUScfg(0 to desc'length) := (others => ((others => ' '),INPUT,PART,0,0,0));
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variable addr, num, vpos :natural := 0;
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file fid :text open write_mode is fname;
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variable l : line;
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variable c : character;
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function \size\(arg :natural) return natural is begin
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for index in 1 to 30 loop
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if (2**index>arg) then return(index); end if;
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end loop;
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return (31);
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end function;
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begin
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-- bus configuration
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for i in 0 to desc'length-1 loop
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num := (desc(i).size-1)/dsize+1;
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vBUS(i+1).name := desc(i).name;
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vBUS(i+1).dir := desc(i).dir;
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vBUS(i+1).addr := addr;
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vBUS(i+1).size := desc(i).size;
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vBUS(i+1).vpos := vpos;
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vBUS(i+1).mode := desc(i).mode;
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addr := addr + num;
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if (desc(i).dir=OUTPUT) then
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case desc(i).mode is
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when PART => vpos := vpos + num;
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when PREG => vpos := vpos + desc(i).size + num;
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when WORD => vpos := vpos + (num-1)*dsize + 1;
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when WREG => vpos := vpos + desc(i).size + (num-1)*dsize + 1;
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end case;
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else
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case desc(i).mode is
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when PART => vpos := vpos + desc(i).size + num;
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when PREG => vpos := vpos + 2*desc(i).size + num;
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when WORD => vpos := vpos + 2*desc(i).size + 1; if (num>1) then vpos := vpos - dsize; end if;
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when WREG => vpos := vpos + 2*desc(i).size + 1;
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end case;
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end if;
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end loop;
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vBUS(0).addr := asize;
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vBUS(0).size := dsize;
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vBUS(0).vpos := vpos+dsize;
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-- bus configuration checking and description file generation
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assert (addr>0) report "vBUScfg: empty configuration" severity warning;
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assert (\size\(addr-1)<=asize) report "vBUScfg: address size exceeded" severity error;
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write(l,string'("<?xml version=""1.0"" encoding=""ISO-8859-1"" ?>"));
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writeline(fid,l);
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write(l,string'("<bus name=""vBUS"" addr="""&integer'image(vBUS(0).addr)&""" data="""&integer'image(vBUS(0).size)&""">"));
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writeline(fid,l);
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vpos := TvBUSnodeCfg.name'length;
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for i in 1 to vBUS'length-1 loop
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for j in i+1 to vBUS'length-1 loop
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assert (vBUS(i).name /= vBUS(0).name) report "vBUScfg: empty name" severity error;
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assert (vBUS(i).name /= vBUS(j).name) report "vBUScfg: names duplicate" severity error;
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end loop;
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num := vpos;
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for j in 1 to vpos loop
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if (vBUS(i).name(j)=' ') then
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num := j-1;
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assert (vBUS(i).name(j to vpos) = vBUS(0).name(j to vpos)) report "vBUScfg: wrong name" severity error;
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exit;
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end if;
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end loop;
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if vBUS(i).dir=INPUT then c:='r'; else c:='w'; end if;
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write(l,string'(" <node name="""&vBUS(i).name(1 to num)&""" permission="""&c&""" addr="""&
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integer'image(vBUS(i).addr)&""" size="""&integer'image(vBUS(i).size)&"""/>"));
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writeline(fid,l);
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end loop;
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write(l,string'("</bus>"));
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writeline(fid,l);
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return (vBUS);
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end function;
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function vBUSlength(cfg :TvBUScfg) return natural is
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begin
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return(cfg(0).vpos);
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end function;
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function \vBUSnodeIdx\(name :string; cfg :TvBUScfg) return natural is
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variable n :string(1 to TvBUSnodeCfg.name'length);
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begin
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n := (others => ' ');
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n(1 to name'length) := name;
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for i in 1 to cfg'length-1 loop
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if(cfg(i).name=n) then return(i); end if;
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end loop;
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return(0);
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end function;
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function vBUSnodeWordSize(name :string; cfg :TvBUScfg) return natural is
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constant n: natural := \vBUSnodeIdx\(name,cfg);
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begin
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if (n>0) then return(cfg(n).size); end if;
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assert (false) report "vBUSnodeSize: node <" & name & "> not exist" severity error;
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return (0);
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end function;
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function vBUSnodeOutputData(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
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constant n :natural := \vBUSnodeIdx\(name,cfg);
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variable d :std_logic_vector(cfg(n).size-1 downto 0);
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variable dv, mv, nv, pv, sv :natural;
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begin
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if (n>0) then
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if (cfg(n).dir=OUTPUT) then
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d := (others => '0');
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dv := cfg(0).size; mv := dv;
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nv := (cfg(n).size-1)/cfg(0).size+1;
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pv := cfg(n).vpos;
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sv := cfg(n).size;
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for p in 0 to nv-1 loop
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if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
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case cfg(n).mode is
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when PART =>
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d(p*dv+mv-1 downto p*dv) := vBUS(cfg(0).vpos-dv+mv-1 downto cfg(0).vpos-dv);
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when PREG =>
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d(p*dv+mv-1 downto p*dv) := vBUS(pv+p*dv+mv-1 downto pv+p*dv);
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when WORD =>
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if (nv>1 and p<nv-1) then
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d((p+1)*dv-1 downto p*dv) := vBUS(pv+(p+1)*dv-1 downto pv+p*dv);
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else
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d(p*dv+mv-1 downto p*dv) := vBUS(cfg(0).vpos-dv+mv-1 downto cfg(0).vpos-dv);
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end if;
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when WREG =>
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if (nv>1 and p<nv-1) then
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d((p+1)*dv-1 downto p*dv) := vBUS(pv+sv+(p+1)*dv-1 downto pv+sv+p*dv);
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else
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d(p*dv+mv-1 downto p*dv) := vBUS(pv+p*dv+mv-1 downto pv+p*dv);
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end if;
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end case;
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end loop;
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return(d);
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else
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report "vBUSnodeWrData: node <" & name & "> is read only" severity error;
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end if;
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else
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report "vBUSnodeWrData: node <" & name & "> not exist" severity error;
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end if;
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return ("");
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end function;
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function vBUSnodeOutputEnable(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
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constant n :natural := \vBUSnodeIdx\(name,cfg);
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variable m :std_logic_vector(cfg(n).size-1 downto 0);
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variable dv, mv, nv, pv, sv :natural;
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begin
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if (n>0) then
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if (cfg(n).dir=OUTPUT) then
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m := (others => '0');
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dv := cfg(0).size; mv := dv;
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nv := (cfg(n).size-1)/cfg(0).size+1;
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pv := cfg(n).vpos;
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sv := cfg(n).size;
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for p in 0 to nv-1 loop
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if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
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case cfg(n).mode is
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when PART =>
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m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+p));
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when PREG =>
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m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+sv+p));
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when WORD =>
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if (p=nv-1) then
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m := (others => vBUS(pv+(nv-1)*dv));
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end if;
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when WREG =>
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if (p=nv-1) then
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m := (others => vBUS(pv+sv+(nv-1)*dv));
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end if;
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end case;
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end loop;
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return(m);
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else
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report "vBUSnodeWrEna: node <" & name & "> is read only" severity error;
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end if;
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else
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report "vBUSnodeWrEna: node <" & name & "> not exist" severity error;
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end if;
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return ("");
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end function;
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249 |
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250 |
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function vBUSnodeInputData(name :string; cfg :TvBUScfg; vBUS, data :std_logic_vector) return std_logic_vector is
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constant n: natural := \vBUSnodeIdx\(name,cfg);
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constant d: std_logic_vector(data'length-1 downto 0) := data;
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variable v: std_logic_vector(vBUS'range);
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begin
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255 |
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if (n>0) then
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if (cfg(n).dir=INPUT) then
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257 |
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v := (others => 'Z');
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258 |
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v(cfg(n).vpos+1*cfg(n).size-1 downto 0*cfg(n).size+cfg(n).vpos) := d;
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259 |
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return(v);
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260 |
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else
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261 |
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report "vBUSnodeRdData: node <" & name & "> is write only" severity error;
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262 |
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end if;
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263 |
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else
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264 |
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report "vBUSnodeRdData: node <" & name & "> not exist" severity error;
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265 |
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end if;
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266 |
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return ("");
|
267 |
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end function;
|
268 |
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269 |
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function vBUSnodeInputEnable(name :string; cfg :TvBUScfg; vBUS :std_logic_vector) return std_logic_vector is
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270 |
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constant n :natural := \vBUSnodeIdx\(name,cfg);
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271 |
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variable m :std_logic_vector(cfg(n).size-1 downto 0);
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272 |
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variable dv, mv, nv, pv, sv :natural;
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273 |
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begin
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274 |
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if (n>0) then
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275 |
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if (cfg(n).dir=INPUT) then
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276 |
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m := (others => '0');
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277 |
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dv := cfg(0).size; mv := dv;
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278 |
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nv := (cfg(n).size-1)/cfg(0).size+1;
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279 |
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pv := cfg(n).vpos;
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280 |
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sv := cfg(n).size;
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281 |
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for p in 0 to nv-1 loop
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282 |
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if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
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283 |
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case cfg(n).mode is
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284 |
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when PART =>
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285 |
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m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+sv+p));
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286 |
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when PREG =>
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287 |
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m(p*dv+mv-1 downto p*dv) := (others => vBUS(pv+2*sv+p));
|
288 |
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when WORD =>
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289 |
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if (nv=1) then
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290 |
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m := (others => vBUS(pv+sv));
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291 |
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else
|
292 |
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m := (others => vBUS(pv+2*sv-dv));
|
293 |
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end if;
|
294 |
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when WREG =>
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295 |
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if (p=nv-1) then
|
296 |
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m := (others => vBUS(pv+2*sv));
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297 |
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end if;
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298 |
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end case;
|
299 |
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end loop;
|
300 |
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return(m);
|
301 |
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else
|
302 |
|
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report "vBUSnodeRdEna: node <" & name & "> is write only" severity error;
|
303 |
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end if;
|
304 |
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else
|
305 |
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report "vBUSnodeRdEna: node <" & name & "> not exist" severity error;
|
306 |
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end if;
|
307 |
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return ("");
|
308 |
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end function;
|
309 |
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|
310 |
|
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end package body;
|
311 |
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|
312 |
|
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---------------------------------------------------------------------------
|
313 |
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|
314 |
|
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library ieee;
|
315 |
|
|
use ieee.std_logic_1164.all;
|
316 |
|
|
use ieee.std_logic_arith.all;
|
317 |
|
|
use work.vBUS.all;
|
318 |
|
|
|
319 |
|
|
entity vBUSinterface is
|
320 |
|
|
generic (
|
321 |
|
|
vBUScfg :TvBUScfg
|
322 |
|
|
);
|
323 |
|
|
port(
|
324 |
|
|
resetN :in std_logic;
|
325 |
|
|
enableN :in std_logic;
|
326 |
|
|
strobeN :in std_logic;
|
327 |
|
|
readN :in std_logic;
|
328 |
|
|
addr :in std_logic_vector;
|
329 |
|
|
data_wr :in std_logic_vector;
|
330 |
|
|
data_rd :out std_logic_vector;
|
331 |
|
|
vbus :inout std_logic_vector
|
332 |
|
|
);
|
333 |
|
|
end entity vBUSinterface;
|
334 |
|
|
|
335 |
|
|
architecture behaviour of vBUSinterface is
|
336 |
|
|
|
337 |
|
|
signal vbus_awr, vbus_swr, vbus_ard, vbus_srd :std_logic_vector(vbus'range) := (others => '0');
|
338 |
|
|
|
339 |
|
|
begin
|
340 |
|
|
|
341 |
|
|
async_wr: process (enableN, readN, addr, vbus) is
|
342 |
|
|
variable bv :std_logic_vector(vbus'range);
|
343 |
|
|
variable av :std_logic;
|
344 |
|
|
variable dv, nv, pv, sv :natural;
|
345 |
|
|
begin
|
346 |
|
|
bv := (others => '0');
|
347 |
|
|
for i in 1 to vBUScfg'length-1 loop
|
348 |
|
|
if (vBUScfg(i).dir=OUTPUT) then
|
349 |
|
|
dv := vBUScfg(0).size;
|
350 |
|
|
nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
|
351 |
|
|
pv := vBUScfg(i).vpos;
|
352 |
|
|
sv := vBUScfg(i).size;
|
353 |
|
|
for p in 0 to nv-1 loop
|
354 |
|
|
if (enableN='0' and readN='1' and vBUScfg(i).addr+p=unsigned(addr)) then av := '1'; else av := '0'; end if;
|
355 |
|
|
case vBUScfg(i).mode is
|
356 |
|
|
when PART =>
|
357 |
|
|
bv(pv+p) := av;
|
358 |
|
|
when PREG =>
|
359 |
|
|
bv(pv+sv+p) := av;
|
360 |
|
|
when WORD =>
|
361 |
|
|
if (p=nv-1) then
|
362 |
|
|
bv(pv+(nv-1)*dv) := av;
|
363 |
|
|
end if;
|
364 |
|
|
when WREG =>
|
365 |
|
|
if (p=nv-1) then
|
366 |
|
|
bv(pv+sv+(nv-1)*dv) := av;
|
367 |
|
|
end if;
|
368 |
|
|
end case;
|
369 |
|
|
end loop;
|
370 |
|
|
end if;
|
371 |
|
|
end loop;
|
372 |
|
|
vbus_awr <= bv;
|
373 |
|
|
end process;
|
374 |
|
|
|
375 |
|
|
sync_wr: process (resetN, strobeN) is
|
376 |
|
|
variable mv, dv, nv, pv, sv :natural;
|
377 |
|
|
begin
|
378 |
|
|
if (resetN='0') then
|
379 |
|
|
vbus_swr <= (others => '0');
|
380 |
|
|
elsif (strobeN'event and strobeN='1') then
|
381 |
|
|
for i in 1 to vBUScfg'length-1 loop
|
382 |
|
|
if (vBUScfg(i).dir=OUTPUT) then
|
383 |
|
|
dv := vBUScfg(0).size; mv := dv;
|
384 |
|
|
nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
|
385 |
|
|
pv := vBUScfg(i).vpos;
|
386 |
|
|
sv := vBUScfg(i).size;
|
387 |
|
|
for p in 0 to nv-1 loop
|
388 |
|
|
if (p=nv-1) then mv := sv-(nv-1)*dv; end if;
|
389 |
|
|
if (enableN='0' and readN='1' and vBUScfg(i).addr+p=unsigned(addr)) then
|
390 |
|
|
case vBUScfg(i).mode is
|
391 |
|
|
when PART =>
|
392 |
|
|
null;
|
393 |
|
|
when PREG =>
|
394 |
|
|
vbus_swr(pv+p*dv+mv-1 downto pv+p*dv) <= data_wr(mv-1 downto 0);
|
395 |
|
|
when WORD =>
|
396 |
|
|
if (p<nv-1) then
|
397 |
|
|
vbus_swr(pv+(p+1)*dv-1 downto pv+p*dv) <= data_wr;
|
398 |
|
|
end if;
|
399 |
|
|
when WREG =>
|
400 |
|
|
vbus_swr(pv+p*dv+mv-1 downto pv+p*dv) <= data_wr(mv-1 downto 0);
|
401 |
|
|
if (nv>1 and p=nv-1) then
|
402 |
|
|
vbus_swr(pv+sv+p*dv-1 downto pv+sv) <= vbus_swr(pv+p*dv-1 downto pv);
|
403 |
|
|
end if;
|
404 |
|
|
end case;
|
405 |
|
|
end if;
|
406 |
|
|
end loop;
|
407 |
|
|
end if;
|
408 |
|
|
end loop;
|
409 |
|
|
end if;
|
410 |
|
|
end process;
|
411 |
|
|
|
412 |
|
|
sync_rd: process (resetN, strobeN) is
|
413 |
|
|
variable mv, dv, nv, pv, sv :natural;
|
414 |
|
|
begin
|
415 |
|
|
if (resetN='0') then
|
416 |
|
|
vbus_srd <= (others => '0');
|
417 |
|
|
elsif (strobeN'event and strobeN='0') then
|
418 |
|
|
for i in 1 to vBUScfg'length-1 loop
|
419 |
|
|
if (vBUScfg(i).dir=INPUT) then
|
420 |
|
|
dv := vBUScfg(0).size; mv := dv;
|
421 |
|
|
nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
|
422 |
|
|
pv := vBUScfg(i).vpos;
|
423 |
|
|
sv := vBUScfg(i).size;
|
424 |
|
|
for p in 0 to nv-1 loop
|
425 |
|
|
if(enableN='0' and readN='0' and vBUScfg(i).addr+p=unsigned(addr)) then
|
426 |
|
|
if (p=nv-1) then mv := sv-(nv-1)*vBUScfg(0).size; end if;
|
427 |
|
|
case vBUScfg(i).mode is
|
428 |
|
|
when PART =>
|
429 |
|
|
null;
|
430 |
|
|
when PREG =>
|
431 |
|
|
vbus_srd(pv+sv+p*dv+mv-1 downto pv+sv+p*dv) <= vbus(pv+p*dv+mv-1 downto pv+p*dv);
|
432 |
|
|
when WORD =>
|
433 |
|
|
if (p=0 and nv>1) then
|
434 |
|
|
vbus_srd(pv+2*sv-dv-1 downto pv+sv) <= vbus(pv+sv-1 downto pv+dv);
|
435 |
|
|
end if;
|
436 |
|
|
when WREG =>
|
437 |
|
|
if (p=0) then
|
438 |
|
|
vbus_srd(pv+2*sv-1 downto pv+1*sv) <= vbus(pv+1*sv-1 downto pv);
|
439 |
|
|
end if;
|
440 |
|
|
end case;
|
441 |
|
|
end if;
|
442 |
|
|
end loop;
|
443 |
|
|
end if;
|
444 |
|
|
end loop;
|
445 |
|
|
end if;
|
446 |
|
|
end process;
|
447 |
|
|
|
448 |
|
|
async_rd: process (enableN, readN, addr, vbus) is
|
449 |
|
|
variable bv :std_logic_vector(vbus'range);
|
450 |
|
|
variable dr, dp, dm :std_logic_vector(vBUScfg(0).size-1 downto 0);
|
451 |
|
|
variable mv, dv, nv, pv, sv :natural;
|
452 |
|
|
begin
|
453 |
|
|
bv := (others => '0');
|
454 |
|
|
dr := (others => '0');
|
455 |
|
|
for i in 1 to vBUScfg'length-1 loop
|
456 |
|
|
if (vBUScfg(i).dir=INPUT) then
|
457 |
|
|
dv := vBUScfg(0).size; mv := dv;
|
458 |
|
|
nv := (vBUScfg(i).size-1)/vBUScfg(0).size+1;
|
459 |
|
|
pv := vBUScfg(i).vpos;
|
460 |
|
|
sv := vBUScfg(i).size;
|
461 |
|
|
dp := (others => '0');
|
462 |
|
|
for p in 0 to nv-1 loop
|
463 |
|
|
if (p=nv-1) then mv := sv-(nv-1)*vBUScfg(0).size; end if;
|
464 |
|
|
dm := (others => '0');
|
465 |
|
|
if (enableN='0' and readN='0' and vBUScfg(i).addr+p=unsigned(addr)) then dm := (others => '1'); end if;
|
466 |
|
|
case vBUScfg(i).mode is
|
467 |
|
|
when PART =>
|
468 |
|
|
bv(pv+sv+p) := dm(0);
|
469 |
|
|
dp(mv-1 downto 0) := vbus(pv+p*dv+mv-1 downto pv+p*dv);
|
470 |
|
|
when PREG =>
|
471 |
|
|
bv(pv+2*sv+p) := dm(0);
|
472 |
|
|
dp(mv-1 downto 0) := vbus(pv+sv+p*dv+mv-1 downto pv+sv+p*dv);
|
473 |
|
|
when WORD =>
|
474 |
|
|
if (p=0) then
|
475 |
|
|
if (nv=1) then
|
476 |
|
|
bv(pv+sv) := dm(0);
|
477 |
|
|
else
|
478 |
|
|
bv(pv+2*sv-dv) := dm(0);
|
479 |
|
|
end if;
|
480 |
|
|
dp(mv-1 downto 0) := vbus(pv+mv-1 downto pv);
|
481 |
|
|
else
|
482 |
|
|
dp(mv-1 downto 0) := vbus(pv+sv+(p-1)*dv+mv-1 downto pv+sv+(p-1)*dv);
|
483 |
|
|
end if;
|
484 |
|
|
when WREG =>
|
485 |
|
|
if (p=0) then
|
486 |
|
|
bv(pv+2*sv) := dm(0);
|
487 |
|
|
end if;
|
488 |
|
|
dp(mv-1 downto 0) := vbus(pv+sv+p*dv+mv-1 downto pv+sv+p*dv);
|
489 |
|
|
end case;
|
490 |
|
|
dr(mv-1 downto 0) := dr(mv-1 downto 0) or (dp(mv-1 downto 0) and dm(mv-1 downto 0));
|
491 |
|
|
end loop;
|
492 |
|
|
end if;
|
493 |
|
|
end loop;
|
494 |
|
|
vbus_ard <= bv;
|
495 |
|
|
data_rd <= dr;
|
496 |
|
|
end process;
|
497 |
|
|
|
498 |
|
|
async_vec: process (vbus_awr, vbus_swr, vbus_srd, vbus_ard, data_wr, enableN, strobeN, resetN) is
|
499 |
|
|
variable bv :std_logic_vector(vbus'range);
|
500 |
|
|
begin
|
501 |
|
|
bv := vbus_awr or vbus_ard or vbus_swr or vbus_srd;
|
502 |
|
|
for i in 1 to vBUScfg'length-1 loop
|
503 |
|
|
if (vBUScfg(i).dir=INPUT) then
|
504 |
|
|
bv(vBUScfg(i).size+vBUScfg(i).vpos-1 downto vBUScfg(i).vpos) := (others => 'Z');
|
505 |
|
|
end if;
|
506 |
|
|
end loop;
|
507 |
|
|
bv(bv'length-1 downto bv'length-vBUScfg(0).size) := data_wr;
|
508 |
|
|
vbus <= bv;
|
509 |
|
|
end process;
|
510 |
|
|
|
511 |
|
|
end behaviour;
|
512 |
|
|
|
513 |
|
|
---------------------------------------------------------------------------
|
514 |
|
|
|
515 |
|
|
library ieee;
|
516 |
|
|
use ieee.std_logic_1164.all;
|
517 |
|
|
use ieee.std_logic_arith.all;
|
518 |
|
|
use work.vBUS.all;
|
519 |
|
|
|
520 |
|
|
entity vBUS_TEST_A_SUM is
|
521 |
|
|
generic (vBUScfg :TvBUScfg);
|
522 |
|
|
port (vBUS :inout std_logic_vector);
|
523 |
|
|
end entity vBUS_TEST_A_SUM;
|
524 |
|
|
|
525 |
|
|
architecture behaviour of vBUS_TEST_A_SUM is
|
526 |
|
|
signal arg1D :std_logic_vector(vBUSnodeWordSize("arg1", vBUScfg)-1 downto 0);
|
527 |
|
|
signal arg2D :std_logic_vector(vBUSnodeWordSize("arg2", vBUScfg)-1 downto 0);
|
528 |
|
|
signal sumD :std_logic_vector(vBUSnodeWordSize("sum", vBUScfg)-1 downto 0);
|
529 |
|
|
begin
|
530 |
|
|
sumD <= unsigned(arg1D) + unsigned(arg2D);
|
531 |
|
|
arg1D <= vBUSnodeOutputData("arg1", vBUScfg, vBUS);
|
532 |
|
|
arg2D <= vBUSnodeOutputData("arg2", vBUScfg, vBUS);
|
533 |
|
|
vBUS <= vBUSnodeInputData ("sum", vBUScfg, vBUS, sumD);
|
534 |
|
|
end behaviour;
|
535 |
|
|
|
536 |
|
|
---------------------------------------------------------------------------
|
537 |
|
|
|
538 |
|
|
library ieee;
|
539 |
|
|
use ieee.std_logic_1164.all;
|
540 |
|
|
use ieee.std_logic_arith.all;
|
541 |
|
|
use work.vBUS.all;
|
542 |
|
|
|
543 |
|
|
entity vBUS_TEST_A_MULT is
|
544 |
|
|
generic (vBUScfg :TvBUScfg);
|
545 |
|
|
port (vBUS :inout std_logic_vector);
|
546 |
|
|
end entity vBUS_TEST_A_MULT;
|
547 |
|
|
|
548 |
|
|
architecture behaviour of vBUS_TEST_A_MULT is
|
549 |
|
|
signal arg1D :std_logic_vector(vBUSnodeWordSize("arg1", vBUScfg)-1 downto 0);
|
550 |
|
|
signal arg2D :std_logic_vector(vBUSnodeWordSize("arg2", vBUScfg)-1 downto 0);
|
551 |
|
|
signal multD :std_logic_vector(vBUSnodeWordSize("mult", vBUScfg)-1 downto 0);
|
552 |
|
|
begin
|
553 |
|
|
multD <= unsigned(arg1D) * unsigned(arg2D);
|
554 |
|
|
arg1D <= vBUSnodeOutputData("arg1", vBUScfg, vBUS);
|
555 |
|
|
arg2D <= vBUSnodeOutputData("arg2", vBUScfg, vBUS);
|
556 |
|
|
vBUS <= vBUSnodeInputData ("mult", vBUScfg, vBUS, multD);
|
557 |
|
|
end behaviour;
|
558 |
|
|
|
559 |
|
|
---------------------------------------------------------------------------
|
560 |
|
|
|
561 |
|
|
library ieee;
|
562 |
|
|
use ieee.std_logic_1164.all;
|
563 |
|
|
use ieee.std_logic_arith.all;
|
564 |
|
|
use work.vBUS.all;
|
565 |
|
|
|
566 |
|
|
entity vBUS_TEST_B is
|
567 |
|
|
generic (
|
568 |
|
|
ADDR_WIDTH :natural := 4;
|
569 |
|
|
DATA_WIDTH :natural := 4
|
570 |
|
|
);
|
571 |
|
|
port(
|
572 |
|
|
resetN :in std_logic;
|
573 |
|
|
enableN :in std_logic;
|
574 |
|
|
strobeN :in std_logic;
|
575 |
|
|
readN :in std_logic;
|
576 |
|
|
addr :in std_logic_vector(ADDR_WIDTH-1 downto 0);
|
577 |
|
|
data_wr :in std_logic_vector(DATA_WIDTH-1 downto 0);
|
578 |
|
|
data_rd :out std_logic_vector(DATA_WIDTH-1 downto 0)
|
579 |
|
|
);
|
580 |
|
|
end entity vBUS_TEST_B;
|
581 |
|
|
|
582 |
|
|
architecture behaviour of vBUS_TEST_B is
|
583 |
|
|
|
584 |
|
|
constant vBUSdesc :TvBUSdesc := (vBUSnodeDesc("arg1", OUTPUT, WREG, 2*ADDR_WIDTH),
|
585 |
|
|
vBUSnodeDesc("arg2", OUTPUT, WREG, 2*ADDR_WIDTH),
|
586 |
|
|
vBUSnodeDesc("mult", INPUT, PART, 4*ADDR_WIDTH),
|
587 |
|
|
vBUSnodeDesc("sum", INPUT, PART, 2*ADDR_WIDTH));
|
588 |
|
|
constant vBUScfg :TvBUScfg := vBUScreator(ADDR_WIDTH, DATA_WIDTH, vBUSdesc, "C:\Home\Pozniak\Projekty\vhdl\tests\src\var\bus_config.xml");
|
589 |
|
|
signal vBUS :std_logic_vector(vBUSlength(vBUScfg)-1 downto 0);
|
590 |
|
|
|
591 |
|
|
begin
|
592 |
|
|
interf: vBUSinterface generic map (vBUScfg) port map (resetN, enableN, strobeN, readN, addr, data_wr, data_rd, vBUS);
|
593 |
|
|
|
594 |
|
|
sum: entity work.vBUS_TEST_A_SUM generic map (vBUScfg) port map (vBUS);
|
595 |
|
|
mult: entity work.vBUS_TEST_A_MULT generic map (vBUScfg) port map (vBUS);
|
596 |
|
|
end behaviour;
|
597 |
|
|
|
598 |
|
|
---------------------------------------------------------------------------
|
599 |
|
|
|
600 |
|
|
library ieee;
|
601 |
|
|
use ieee.std_logic_1164.all;
|
602 |
|
|
use ieee.std_logic_arith.all;
|
603 |
|
|
use work.vBUS.all;
|
604 |
|
|
|
605 |
|
|
entity vBUS_TEST_A is
|
606 |
|
|
generic (
|
607 |
|
|
ADDR_WIDTH :natural := 3;
|
608 |
|
|
DATA_WIDTH :natural := 4;
|
609 |
|
|
ITEM_MODE :TvBUSnodeMode := PART
|
610 |
|
|
);
|
611 |
|
|
port(
|
612 |
|
|
resetN :in std_logic;
|
613 |
|
|
enableN :in std_logic;
|
614 |
|
|
strobeN :in std_logic;
|
615 |
|
|
readN :in std_logic;
|
616 |
|
|
addr :in std_logic_vector(ADDR_WIDTH-1 downto 0);
|
617 |
|
|
data_wr :in std_logic_vector(DATA_WIDTH-1 downto 0);
|
618 |
|
|
data_rd :out std_logic_vector(DATA_WIDTH-1 downto 0);
|
619 |
|
|
sdata_output :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
|
620 |
|
|
sena_output :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
|
621 |
|
|
ldata_output :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
|
622 |
|
|
lena_output :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
|
623 |
|
|
sdata_input :in std_logic_vector(DATA_WIDTH/2-1 downto 0);
|
624 |
|
|
sena_input :out std_logic_vector(DATA_WIDTH/2-1 downto 0);
|
625 |
|
|
ldata_input :in std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0);
|
626 |
|
|
lena_input :out std_logic_vector(5*(DATA_WIDTH/2)-1 downto 0)
|
627 |
|
|
);
|
628 |
|
|
end entity vBUS_TEST_A;
|
629 |
|
|
|
630 |
|
|
architecture behaviour of vBUS_TEST_A is
|
631 |
|
|
constant vBUSdesc :TvBUSdesc := (vBUSnodeDesc("soutput", OUTPUT, ITEM_MODE, sdata_output'length),
|
632 |
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vBUSnodeDesc("loutput", OUTPUT, ITEM_MODE, ldata_output'length),
|
633 |
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vBUSnodeDesc("sinput", INPUT, ITEM_MODE, sdata_input'length),
|
634 |
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vBUSnodeDesc("linput", INPUT, ITEM_MODE, ldata_input'length));
|
635 |
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constant vBUScfg :TvBUScfg := vBUScreator(ADDR_WIDTH, DATA_WIDTH, vBUSdesc, "C:\Home\Pozniak\Projekty\vhdl\tests\src\var\bus_config.xml");
|
636 |
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signal vBUS :std_logic_vector(vBUSlength(vBUScfg)-1 downto 0);
|
637 |
|
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begin
|
638 |
|
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i: vBUSinterface generic map (vBUScfg) port map (resetN, enableN, strobeN, readN, addr, data_wr, data_rd, vBUS);
|
639 |
|
|
|
640 |
|
|
sdata_output <= vBUSnodeOutputData ("soutput", vBUScfg, vBUS);
|
641 |
|
|
sena_output <= vBUSnodeOutputEnable("soutput", vBUScfg, vBUS);
|
642 |
|
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ldata_output <= vBUSnodeOutputData ("loutput", vBUScfg, vBUS);
|
643 |
|
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lena_output <= vBUSnodeOutputEnable("loutput", vBUScfg, vBUS);
|
644 |
|
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vBUS <= vBUSnodeInputData ("sinput", vBUScfg, vBUS, sdata_input);
|
645 |
|
|
sena_input <= vBUSnodeInputEnable ("sinput", vBUScfg, vBUS);
|
646 |
|
|
vBUS <= vBUSnodeInputData ("linput", vBUScfg, vBUS, ldata_input);
|
647 |
|
|
lena_input <= vBUSnodeInputEnable ("linput", vBUScfg, vBUS);
|
648 |
|
|
end behaviour;
|
649 |
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