Subversion Repositories soc_maker

SOCM_CORE

name: ram_wb

description: Onchip-RAM

version: b3

license: LGPL

licensefile:

author:

authormail:

vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb@655 rtl

toplevel: ram_wb_b3

interfaces:

  :wb_ifc: SOCM_IFC

    name: wishbone_sl

    dir: 1

    version: "b3"

    ports:

      :wb_adr_i: SOCM_PORT

        len: 32

        defn: adr

      :wb_bte_i: SOCM_PORT

        len: 2

        defn: bte

      :wb_cti_i: SOCM_PORT

        len: 3

        defn: cti

      :wb_cyc_i: SOCM_PORT

        len: 1

        defn: cyc

      :wb_dat_i: SOCM_PORT

        len: 32

        defn: dat_o

      :wb_sel_i: SOCM_PORT

        len: 4

        defn: sel

      :wb_stb_i: SOCM_PORT

        len: 1

        defn: stb

      :wb_we_i: SOCM_PORT

        len: 1

        defn: we

      :wb_ack_o: SOCM_PORT

        len: 1

        defn: ack

      :wb_err_o: SOCM_PORT

        len: 1

        defn: err

      :wb_rty_o: SOCM_PORT

        len: 1

        defn: rty

      :wb_dat_o: SOCM_PORT

        len: 32

        defn: dat_i

      :wb_clk_i: SOCM_PORT

        len: 1

        defn: clk

      :wb_rst_i: SOCM_PORT

        len: 1

        defn: rst

hdlfiles:

  :ram_wb_b3: SOCM_HDL_FILE

    use_syn: true

    use_sim: true

    type: verilog

    path: rtl/ram_wb_b3.v