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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Xess Traffic Cop                                            ////

////                                                              ////

////  This file is part of the OR1K test application              ////

////  http://www.opencores.org/cores/or1k/                        ////

////                                                              ////

////  Description                                                 ////

////  This block connectes the RISC and peripheral controller     ////

////  cores together.                                             ////

////                                                              ////

////  To Do:                                                      ////

////   - nothing really                                           ////

////                                                              ////

////  Author(s):                                                  ////

////      - Damjan Lampret, lampret@opencores.org                 ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2002 OpenCores                                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: tc_top.v,v $

// Revision 1.4  2004/04/05 08:44:34  lampret

// Merged branch_qmem into main tree.

//

// Revision 1.2  2002/03/29 20:57:30  lampret

// Removed unused ports wb_clki and wb_rst_i

//

// Revision 1.1.1.1  2002/03/21 16:55:44  lampret

// First import of the "new" XESS XSV environment.

//

//

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

//

// Width of address bus

//

`define TC_AW           32

//

// Width of data bus

//

`define TC_DW           32

//

// Width of byte select bus

//

`define TC_BSW          4

//

// Width of WB target inputs (coming from WB slave)

//

// data bus width + ack + err

//

`define TC_TIN_W        `TC_DW+1+1

//

// Width of WB initiator inputs (coming from WB masters)

//

// cyc + stb + address bus width +

// byte select bus width + we + data bus width

//

`define TC_IIN_W        1+1+`TC_AW+`TC_BSW+1+`TC_DW

//

// Traffic Cop Top

//

module minsoc_tc_top (

        wb_clk_i,

        wb_rst_i,

   i0_wb_clk_o,

   i0_wb_rst_o,

        i0_wb_cyc_i,

        i0_wb_stb_i,

        i0_wb_adr_i,

        i0_wb_sel_i,

        i0_wb_we_i,

        i0_wb_dat_i,

        i0_wb_dat_o,

        i0_wb_ack_o,

        i0_wb_err_o,

   i1_wb_clk_o,

   i1_wb_rst_o,

        i1_wb_cyc_i,

        i1_wb_stb_i,

        i1_wb_adr_i,

        i1_wb_sel_i,

        i1_wb_we_i,

        i1_wb_dat_i,

        i1_wb_dat_o,

        i1_wb_ack_o,

        i1_wb_err_o,

   i2_wb_clk_o,

   i2_wb_rst_o,

        i2_wb_cyc_i,

        i2_wb_stb_i,

        i2_wb_adr_i,

        i2_wb_sel_i,

        i2_wb_we_i,

        i2_wb_dat_i,

        i2_wb_dat_o,

        i2_wb_ack_o,

        i2_wb_err_o,

   i3_wb_clk_o,

   i3_wb_rst_o,

        i3_wb_cyc_i,

        i3_wb_stb_i,

        i3_wb_adr_i,

        i3_wb_sel_i,

        i3_wb_we_i,

        i3_wb_dat_i,

        i3_wb_dat_o,

        i3_wb_ack_o,

        i3_wb_err_o,

   i4_wb_clk_o,

   i4_wb_rst_o,

        i4_wb_cyc_i,

        i4_wb_stb_i,

        i4_wb_adr_i,

        i4_wb_sel_i,

        i4_wb_we_i,

        i4_wb_dat_i,

        i4_wb_dat_o,

        i4_wb_ack_o,

        i4_wb_err_o,

   i5_wb_clk_o,

   i5_wb_rst_o,

        i5_wb_cyc_i,

        i5_wb_stb_i,

        i5_wb_adr_i,

        i5_wb_sel_i,

        i5_wb_we_i,

        i5_wb_dat_i,

        i5_wb_dat_o,

        i5_wb_ack_o,

        i5_wb_err_o,

   i6_wb_clk_o,

   i6_wb_rst_o,

        i6_wb_cyc_i,

        i6_wb_stb_i,

        i6_wb_adr_i,

        i6_wb_sel_i,

        i6_wb_we_i,

        i6_wb_dat_i,

        i6_wb_dat_o,

        i6_wb_ack_o,

        i6_wb_err_o,

   i7_wb_clk_o,

   i7_wb_rst_o,

        i7_wb_cyc_i,

        i7_wb_stb_i,

        i7_wb_adr_i,

        i7_wb_sel_i,

        i7_wb_we_i,

        i7_wb_dat_i,

        i7_wb_dat_o,

        i7_wb_ack_o,

        i7_wb_err_o,

   t0_wb_clk_o,

   t0_wb_rst_o,

        t0_wb_cyc_o,

        t0_wb_stb_o,

        t0_wb_adr_o,

        t0_wb_sel_o,

        t0_wb_we_o,

        t0_wb_dat_o,

        t0_wb_dat_i,

        t0_wb_ack_i,

        t0_wb_err_i,

   t1_wb_clk_o,

   t1_wb_rst_o,

        t1_wb_cyc_o,

        t1_wb_stb_o,

        t1_wb_adr_o,

        t1_wb_sel_o,

        t1_wb_we_o,

        t1_wb_dat_o,

        t1_wb_dat_i,

        t1_wb_ack_i,

        t1_wb_err_i,

   t2_wb_clk_o,

   t2_wb_rst_o,

        t2_wb_cyc_o,

        t2_wb_stb_o,

        t2_wb_adr_o,

        t2_wb_sel_o,

        t2_wb_we_o,

        t2_wb_dat_o,

        t2_wb_dat_i,

        t2_wb_ack_i,

        t2_wb_err_i,

   t3_wb_clk_o,

   t3_wb_rst_o,

        t3_wb_cyc_o,

        t3_wb_stb_o,

        t3_wb_adr_o,

        t3_wb_sel_o,

        t3_wb_we_o,

        t3_wb_dat_o,

        t3_wb_dat_i,

        t3_wb_ack_i,

        t3_wb_err_i,

   t4_wb_clk_o,

   t4_wb_rst_o,

        t4_wb_cyc_o,

        t4_wb_stb_o,

        t4_wb_adr_o,

        t4_wb_sel_o,

        t4_wb_we_o,

        t4_wb_dat_o,

        t4_wb_dat_i,

        t4_wb_ack_i,

        t4_wb_err_i,

   t5_wb_clk_o,

   t5_wb_rst_o,

        t5_wb_cyc_o,

        t5_wb_stb_o,

        t5_wb_adr_o,

        t5_wb_sel_o,

        t5_wb_we_o,

        t5_wb_dat_o,

        t5_wb_dat_i,

        t5_wb_ack_i,

        t5_wb_err_i,

   t6_wb_clk_o,

   t6_wb_rst_o,

        t6_wb_cyc_o,

        t6_wb_stb_o,

        t6_wb_adr_o,

        t6_wb_sel_o,

        t6_wb_we_o,

        t6_wb_dat_o,

        t6_wb_dat_i,

        t6_wb_ack_i,

        t6_wb_err_i,

   t7_wb_clk_o,

   t7_wb_rst_o,

        t7_wb_cyc_o,

        t7_wb_stb_o,

        t7_wb_adr_o,

        t7_wb_sel_o,

        t7_wb_we_o,

        t7_wb_dat_o,

        t7_wb_dat_i,

        t7_wb_ack_i,

        t7_wb_err_i,

   t8_wb_clk_o,

   t8_wb_rst_o,

        t8_wb_cyc_o,

        t8_wb_stb_o,

        t8_wb_adr_o,

        t8_wb_sel_o,

        t8_wb_we_o,

        t8_wb_dat_o,

        t8_wb_dat_i,

        t8_wb_ack_i,

        t8_wb_err_i

);

//

// Parameters

//

parameter               t0_addr_w = 4;

parameter               t0_addr = 4'd8;

parameter               t1_addr_w = 4;

parameter               t1_addr = 4'd0;

parameter               t28c_addr_w = 4;

parameter               t28_addr = 4'd0;

parameter               t28i_addr_w = 4;

parameter               t2_addr = 4'd1;

parameter               t3_addr = 4'd2;

parameter               t4_addr = 4'd3;

parameter               t5_addr = 4'd4;

parameter               t6_addr = 4'd5;

parameter               t7_addr = 4'd6;

parameter               t8_addr = 4'd7;

//

// I/O Ports

//

input                   wb_clk_i;

input                   wb_rst_i;

//

// WB slave i/f connecting initiator 0

//

input                   i0_wb_cyc_i;

input                   i0_wb_stb_i;

input   [`TC_AW-1:0]     i0_wb_adr_i;

input   [`TC_BSW-1:0]    i0_wb_sel_i;

input                   i0_wb_we_i;

input   [`TC_DW-1:0]     i0_wb_dat_i;

output  [`TC_DW-1:0]     i0_wb_dat_o;

output                  i0_wb_ack_o;

output                  i0_wb_err_o;

//

// WB slave i/f connecting initiator 1

//

input                   i1_wb_cyc_i;

input                   i1_wb_stb_i;

input   [`TC_AW-1:0]     i1_wb_adr_i;

input   [`TC_BSW-1:0]    i1_wb_sel_i;

input                   i1_wb_we_i;

input   [`TC_DW-1:0]     i1_wb_dat_i;

output  [`TC_DW-1:0]     i1_wb_dat_o;

output                  i1_wb_ack_o;

output                  i1_wb_err_o;

//

// WB slave i/f connecting initiator 2

//

input                   i2_wb_cyc_i;

input                   i2_wb_stb_i;

input   [`TC_AW-1:0]     i2_wb_adr_i;

input   [`TC_BSW-1:0]    i2_wb_sel_i;

input                   i2_wb_we_i;

input   [`TC_DW-1:0]     i2_wb_dat_i;

output  [`TC_DW-1:0]     i2_wb_dat_o;

output                  i2_wb_ack_o;

output                  i2_wb_err_o;

//

// WB slave i/f connecting initiator 3

//

input                   i3_wb_cyc_i;

input                   i3_wb_stb_i;

input   [`TC_AW-1:0]     i3_wb_adr_i;

input   [`TC_BSW-1:0]    i3_wb_sel_i;

input                   i3_wb_we_i;

input   [`TC_DW-1:0]     i3_wb_dat_i;

output  [`TC_DW-1:0]     i3_wb_dat_o;

output                  i3_wb_ack_o;

output                  i3_wb_err_o;

//

// WB slave i/f connecting initiator 4

//

input                   i4_wb_cyc_i;

input                   i4_wb_stb_i;

input   [`TC_AW-1:0]     i4_wb_adr_i;

input   [`TC_BSW-1:0]    i4_wb_sel_i;

input                   i4_wb_we_i;

input   [`TC_DW-1:0]     i4_wb_dat_i;

output  [`TC_DW-1:0]     i4_wb_dat_o;

output                  i4_wb_ack_o;

output                  i4_wb_err_o;

//

// WB slave i/f connecting initiator 5

//

input                   i5_wb_cyc_i;

input                   i5_wb_stb_i;

input   [`TC_AW-1:0]     i5_wb_adr_i;

input   [`TC_BSW-1:0]    i5_wb_sel_i;

input                   i5_wb_we_i;

input   [`TC_DW-1:0]     i5_wb_dat_i;

output  [`TC_DW-1:0]     i5_wb_dat_o;

output                  i5_wb_ack_o;

output                  i5_wb_err_o;

//

// WB slave i/f connecting initiator 6

//

input                   i6_wb_cyc_i;

input                   i6_wb_stb_i;

input   [`TC_AW-1:0]     i6_wb_adr_i;

input   [`TC_BSW-1:0]    i6_wb_sel_i;

input                   i6_wb_we_i;

input   [`TC_DW-1:0]     i6_wb_dat_i;

output  [`TC_DW-1:0]     i6_wb_dat_o;

output                  i6_wb_ack_o;

output                  i6_wb_err_o;

//

// WB slave i/f connecting initiator 7

//

input                   i7_wb_cyc_i;

input                   i7_wb_stb_i;

input   [`TC_AW-1:0]     i7_wb_adr_i;

input   [`TC_BSW-1:0]    i7_wb_sel_i;

input                   i7_wb_we_i;

input   [`TC_DW-1:0]     i7_wb_dat_i;

output  [`TC_DW-1:0]     i7_wb_dat_o;

output                  i7_wb_ack_o;

output                  i7_wb_err_o;

//

// WB master i/f connecting target 0

//

output                  t0_wb_cyc_o;

output                  t0_wb_stb_o;

output  [`TC_AW-1:0]     t0_wb_adr_o;

output  [`TC_BSW-1:0]    t0_wb_sel_o;

output                  t0_wb_we_o;

output  [`TC_DW-1:0]     t0_wb_dat_o;

input   [`TC_DW-1:0]     t0_wb_dat_i;

input                   t0_wb_ack_i;

input                   t0_wb_err_i;

//

// WB master i/f connecting target 1

//

output                  t1_wb_cyc_o;

output                  t1_wb_stb_o;

output  [`TC_AW-1:0]     t1_wb_adr_o;

output  [`TC_BSW-1:0]    t1_wb_sel_o;

output                  t1_wb_we_o;

output  [`TC_DW-1:0]     t1_wb_dat_o;

input   [`TC_DW-1:0]     t1_wb_dat_i;

input                   t1_wb_ack_i;

input                   t1_wb_err_i;

//

// WB master i/f connecting target 2

//

output                  t2_wb_cyc_o;

output                  t2_wb_stb_o;

output  [`TC_AW-1:0]     t2_wb_adr_o;

output  [`TC_BSW-1:0]    t2_wb_sel_o;

output                  t2_wb_we_o;

output  [`TC_DW-1:0]     t2_wb_dat_o;

input   [`TC_DW-1:0]     t2_wb_dat_i;

input                   t2_wb_ack_i;

input                   t2_wb_err_i;

//

// WB master i/f connecting target 3

//

output                  t3_wb_cyc_o;

output                  t3_wb_stb_o;

output  [`TC_AW-1:0]     t3_wb_adr_o;

output  [`TC_BSW-1:0]    t3_wb_sel_o;

output                  t3_wb_we_o;

output  [`TC_DW-1:0]     t3_wb_dat_o;

input   [`TC_DW-1:0]     t3_wb_dat_i;

input                   t3_wb_ack_i;

input                   t3_wb_err_i;

//

// WB master i/f connecting target 4

//

output                  t4_wb_cyc_o;

output                  t4_wb_stb_o;

output  [`TC_AW-1:0]     t4_wb_adr_o;

output  [`TC_BSW-1:0]    t4_wb_sel_o;

output                  t4_wb_we_o;

output  [`TC_DW-1:0]     t4_wb_dat_o;

input   [`TC_DW-1:0]     t4_wb_dat_i;

input                   t4_wb_ack_i;

input                   t4_wb_err_i;

//

// WB master i/f connecting target 5

//

output                  t5_wb_cyc_o;

output                  t5_wb_stb_o;

output  [`TC_AW-1:0]     t5_wb_adr_o;

output  [`TC_BSW-1:0]    t5_wb_sel_o;

output                  t5_wb_we_o;

output  [`TC_DW-1:0]     t5_wb_dat_o;

input   [`TC_DW-1:0]     t5_wb_dat_i;

input                   t5_wb_ack_i;

input                   t5_wb_err_i;

//

// WB master i/f connecting target 6

//

output                  t6_wb_cyc_o;

output                  t6_wb_stb_o;

output  [`TC_AW-1:0]     t6_wb_adr_o;

output  [`TC_BSW-1:0]    t6_wb_sel_o;

output                  t6_wb_we_o;

output  [`TC_DW-1:0]     t6_wb_dat_o;

input   [`TC_DW-1:0]     t6_wb_dat_i;

input                   t6_wb_ack_i;

input                   t6_wb_err_i;

//

// WB master i/f connecting target 7

//

output                  t7_wb_cyc_o;

output                  t7_wb_stb_o;

output  [`TC_AW-1:0]     t7_wb_adr_o;

output  [`TC_BSW-1:0]    t7_wb_sel_o;

output                  t7_wb_we_o;

output  [`TC_DW-1:0]     t7_wb_dat_o;

input   [`TC_DW-1:0]     t7_wb_dat_i;

input                   t7_wb_ack_i;

input                   t7_wb_err_i;

//

// WB master i/f connecting target 8

//

output                  t8_wb_cyc_o;

output                  t8_wb_stb_o;

output  [`TC_AW-1:0]     t8_wb_adr_o;

output  [`TC_BSW-1:0]    t8_wb_sel_o;

output                  t8_wb_we_o;

output  [`TC_DW-1:0]     t8_wb_dat_o;

input   [`TC_DW-1:0]     t8_wb_dat_i;

input                   t8_wb_ack_i;

input                   t8_wb_err_i;

output i0_wb_clk_o;

output i0_wb_rst_o;

output i1_wb_clk_o;

output i1_wb_rst_o;

output i2_wb_clk_o;

output i2_wb_rst_o;

output i3_wb_clk_o;

output i3_wb_rst_o;

output i4_wb_clk_o;

output i4_wb_rst_o;

output i5_wb_clk_o;

output i5_wb_rst_o;

output i6_wb_clk_o;

output i6_wb_rst_o;

output i7_wb_clk_o;

output i7_wb_rst_o;

output t0_wb_clk_o;

output t0_wb_rst_o;

output t1_wb_clk_o;

output t1_wb_rst_o;

output t2_wb_clk_o;

output t2_wb_rst_o;

output t3_wb_clk_o;

output t3_wb_rst_o;

output t4_wb_clk_o;

output t4_wb_rst_o;

output t5_wb_clk_o;

output t5_wb_rst_o;

output t6_wb_clk_o;

output t6_wb_rst_o;

output t7_wb_clk_o;

output t7_wb_rst_o;

output t8_wb_clk_o;

output t8_wb_rst_o;

//

// Internal wires & registers

//

//

// Outputs for initiators from both mi_to_st blocks

//

wire    [`TC_DW-1:0]     xi0_wb_dat_o;

wire                    xi0_wb_ack_o;

wire                    xi0_wb_err_o;

wire    [`TC_DW-1:0]     xi1_wb_dat_o;

wire                    xi1_wb_ack_o;

wire                    xi1_wb_err_o;

wire    [`TC_DW-1:0]     xi2_wb_dat_o;

wire                    xi2_wb_ack_o;

wire                    xi2_wb_err_o;

wire    [`TC_DW-1:0]     xi3_wb_dat_o;

wire                    xi3_wb_ack_o;

wire                    xi3_wb_err_o;

wire    [`TC_DW-1:0]     xi4_wb_dat_o;

wire                    xi4_wb_ack_o;

wire                    xi4_wb_err_o;

wire    [`TC_DW-1:0]     xi5_wb_dat_o;

wire                    xi5_wb_ack_o;

wire                    xi5_wb_err_o;

wire    [`TC_DW-1:0]     xi6_wb_dat_o;

wire                    xi6_wb_ack_o;

wire                    xi6_wb_err_o;

wire    [`TC_DW-1:0]     xi7_wb_dat_o;

wire                    xi7_wb_ack_o;

wire                    xi7_wb_err_o;

wire    [`TC_DW-1:0]     yi0_wb_dat_o;

wire                    yi0_wb_ack_o;

wire                    yi0_wb_err_o;

wire    [`TC_DW-1:0]     yi1_wb_dat_o;

wire                    yi1_wb_ack_o;

wire                    yi1_wb_err_o;

wire    [`TC_DW-1:0]     yi2_wb_dat_o;

wire                    yi2_wb_ack_o;

wire                    yi2_wb_err_o;

wire    [`TC_DW-1:0]     yi3_wb_dat_o;

wire                    yi3_wb_ack_o;

wire                    yi3_wb_err_o;

wire    [`TC_DW-1:0]     yi4_wb_dat_o;

wire                    yi4_wb_ack_o;

wire                    yi4_wb_err_o;

wire    [`TC_DW-1:0]     yi5_wb_dat_o;

wire                    yi5_wb_ack_o;

wire                    yi5_wb_err_o;

wire    [`TC_DW-1:0]     yi6_wb_dat_o;

wire                    yi6_wb_ack_o;

wire                    yi6_wb_err_o;

wire    [`TC_DW-1:0]     yi7_wb_dat_o;

wire                    yi7_wb_ack_o;

wire                    yi7_wb_err_o;

//

// Intermediate signals connecting peripheral channel's

// mi_to_st and si_to_mt blocks.

//

wire                    z_wb_cyc_i;

wire                    z_wb_stb_i;

wire    [`TC_AW-1:0]     z_wb_adr_i;

wire    [`TC_BSW-1:0]    z_wb_sel_i;

wire                    z_wb_we_i;

wire    [`TC_DW-1:0]     z_wb_dat_i;

wire    [`TC_DW-1:0]     z_wb_dat_t;

wire                    z_wb_ack_t;

wire                    z_wb_err_t;

//

// Assign clock and resets

//

assign i0_wb_clk_o = wb_clk_i;

assign i0_wb_rst_o = wb_rst_i;

assign i1_wb_clk_o = wb_clk_i;

assign i1_wb_rst_o = wb_rst_i;

assign i2_wb_clk_o = wb_clk_i;

assign i2_wb_rst_o = wb_rst_i;

assign i3_wb_clk_o = wb_clk_i;

assign i3_wb_rst_o = wb_rst_i;

assign i4_wb_clk_o = wb_clk_i;

assign i4_wb_rst_o = wb_rst_i;

assign i5_wb_clk_o = wb_clk_i;

assign i5_wb_rst_o = wb_rst_i;

assign i6_wb_clk_o = wb_clk_i;

assign i6_wb_rst_o = wb_rst_i;

assign i7_wb_clk_o = wb_clk_i;

assign i7_wb_rst_o = wb_rst_i;

assign t0_wb_clk_o = wb_clk_i;

assign t0_wb_rst_o = wb_rst_i;

assign t1_wb_clk_o = wb_clk_i;

assign t1_wb_rst_o = wb_rst_i;

assign t2_wb_clk_o = wb_clk_i;

assign t2_wb_rst_o = wb_rst_i;

assign t3_wb_clk_o = wb_clk_i;

assign t3_wb_rst_o = wb_rst_i;

assign t4_wb_clk_o = wb_clk_i;

assign t4_wb_rst_o = wb_rst_i;

assign t5_wb_clk_o = wb_clk_i;

assign t5_wb_rst_o = wb_rst_i;

assign t6_wb_clk_o = wb_clk_i;

assign t6_wb_rst_o = wb_rst_i;

assign t7_wb_clk_o = wb_clk_i;

assign t7_wb_rst_o = wb_rst_i;

assign t8_wb_clk_o = wb_clk_i;

assign t8_wb_rst_o = wb_rst_i;

//

// Outputs for initiators are ORed from both mi_to_st blocks

//

assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;

assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;