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SOCM_CORE
name: wb_connect
description: A block to connect RISC and peripheral controllers together
version: "1"
license: LGPL
licensefile:
author: Damjan Lampret
authormail: lampret@opencores.org
toplevel: minsoc_tc_top
interfaces:
  :i0: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i0_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i0_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i0_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i0_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i0_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i0_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i0_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i0_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i0_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i1: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i1_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i1_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i1_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i1_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i1_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i1_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i1_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i1_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i1_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i2: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i2_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i2_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i2_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i2_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i2_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i2_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i2_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i2_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i2_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i3: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i3_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i3_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i3_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i3_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i3_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i3_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i3_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i3_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i3_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i4: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i4_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i4_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i4_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i4_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i4_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i4_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i4_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i4_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i4_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i5: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i5_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i5_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i5_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i5_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i5_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i5_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i5_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i5_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i5_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i6: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i6_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i6_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i6_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i6_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i6_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i6_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i6_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i6_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i6_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :i7: SOCM_IFC
    name: wishbone_ma
    dir: 1
    version: "b3"
    ports:
      :i7_wb_cyc_i: SOCM_PORT
        defn: cyc
        len:  1
      :i7_wb_stb_i: SOCM_PORT
        defn: stb
        len:  1
      :i7_wb_adr_i: SOCM_PORT
        defn: adr
        len:  32
      :i7_wb_sel_i: SOCM_PORT
        defn: sel
        len:  1
      :i7_wb_we_i: SOCM_PORT
        defn: we
        len:  1
      :i7_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :i7_wb_dat_o: SOCM_PORT
        defn: dat_o
        len:  32
      :i7_wb_ack_o: SOCM_PORT
        defn: ack
        len:  1
      :i7_wb_err_o: SOCM_PORT
        defn: err
        len:  1
  :t0: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t0_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t0_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t0_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t0_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t0_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t0_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t0_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t0_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t0_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t1: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t1_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t1_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t1_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t1_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t1_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t1_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t1_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t1_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t1_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t2: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t2_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t2_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t2_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t2_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t2_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t2_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t2_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t2_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t2_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t3: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t3_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t3_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t3_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t3_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t3_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t3_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t3_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t3_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t3_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t4: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t4_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t4_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t4_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t4_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t4_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t4_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t4_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t4_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t4_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t5: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t5_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t5_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t5_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t5_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t5_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t5_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t5_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t5_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t5_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t6: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t6_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t6_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t6_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t6_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t6_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t6_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t6_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t6_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t6_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t7: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t7_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t7_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t7_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t7_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t7_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t7_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t7_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t7_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t7_wb_err_i: SOCM_PORT
        defn: err
        len:  1
  :t8: SOCM_IFC
    name: wishbone_sl
    dir: 1
    version: "b3"
    ports:
      :t8_wb_cyc_o: SOCM_PORT
        defn: cyc
        len:  1
      :t8_wb_stb_o: SOCM_PORT
        defn: stb
        len:  1
      :t8_wb_adr_o: SOCM_PORT
        defn: adr
        len:  32
      :t8_wb_sel_o: SOCM_PORT
        defn: sel
        len:  1
      :t8_wb_we_o: SOCM_PORT
        defn: we
        len:  1
      :t8_wb_dat_o: SOCM_PORT
        defn: dat_i
        len:  32
      :t8_wb_dat_i: SOCM_PORT
        defn: dat_i
        len:  32
      :t8_wb_ack_i: SOCM_PORT
        defn: ack
        len:  1
      :t8_wb_err_i: SOCM_PORT
        defn: err
        len:  1
 
 
 
 
hdlfiles:
  :minsoc_tc_top: SOCM_HDL_FILE
    use_syn: true
    use_sim: true
    type: verilog
    path: minsoc_tc_top.v

Line No.	Rev	Author	Line
1	5	feddischso	`SOCM_CORE`
2			`name: wb_connect`
3			`description: A block to connect RISC and peripheral controllers together`
4			`version: "1"`
5			`license: LGPL`
6			`licensefile:`
7			`author: Damjan Lampret`
8			`authormail: lampret@opencores.org`
9			`toplevel: minsoc_tc_top`
10			`interfaces:`
11			`:i0: SOCM_IFC`
12			`name: wishbone_ma`
13			`dir: 1`
14			`version: "b3"`
15			`ports:`
16			`:i0_wb_cyc_i: SOCM_PORT`
17			`defn: cyc`
18			`len: 1`
19			`:i0_wb_stb_i: SOCM_PORT`
20			`defn: stb`
21			`len: 1`
22			`:i0_wb_adr_i: SOCM_PORT`
23			`defn: adr`
24			`len: 32`
25			`:i0_wb_sel_i: SOCM_PORT`
26			`defn: sel`
27			`len: 1`
28			`:i0_wb_we_i: SOCM_PORT`
29			`defn: we`
30			`len: 1`
31			`:i0_wb_dat_i: SOCM_PORT`
32			`defn: dat_i`
33			`len: 32`
34			`:i0_wb_dat_o: SOCM_PORT`
35			`defn: dat_o`
36			`len: 32`
37			`:i0_wb_ack_o: SOCM_PORT`
38			`defn: ack`
39			`len: 1`
40			`:i0_wb_err_o: SOCM_PORT`
41			`defn: err`
42			`len: 1`
43			`:i1: SOCM_IFC`
44			`name: wishbone_ma`
45			`dir: 1`
46			`version: "b3"`
47			`ports:`
48			`:i1_wb_cyc_i: SOCM_PORT`
49			`defn: cyc`
50			`len: 1`
51			`:i1_wb_stb_i: SOCM_PORT`
52			`defn: stb`
53			`len: 1`
54			`:i1_wb_adr_i: SOCM_PORT`
55			`defn: adr`
56			`len: 32`
57			`:i1_wb_sel_i: SOCM_PORT`
58			`defn: sel`
59			`len: 1`
60			`:i1_wb_we_i: SOCM_PORT`
61			`defn: we`
62			`len: 1`
63			`:i1_wb_dat_i: SOCM_PORT`
64			`defn: dat_i`
65			`len: 32`
66			`:i1_wb_dat_o: SOCM_PORT`
67			`defn: dat_o`
68			`len: 32`
69			`:i1_wb_ack_o: SOCM_PORT`
70			`defn: ack`
71			`len: 1`
72			`:i1_wb_err_o: SOCM_PORT`
73			`defn: err`
74			`len: 1`
75			`:i2: SOCM_IFC`
76			`name: wishbone_ma`
77			`dir: 1`
78			`version: "b3"`
79			`ports:`
80			`:i2_wb_cyc_i: SOCM_PORT`
81			`defn: cyc`
82			`len: 1`
83			`:i2_wb_stb_i: SOCM_PORT`
84			`defn: stb`
85			`len: 1`
86			`:i2_wb_adr_i: SOCM_PORT`
87			`defn: adr`
88			`len: 32`
89			`:i2_wb_sel_i: SOCM_PORT`
90			`defn: sel`
91			`len: 1`
92			`:i2_wb_we_i: SOCM_PORT`
93			`defn: we`
94			`len: 1`
95			`:i2_wb_dat_i: SOCM_PORT`
96			`defn: dat_i`
97			`len: 32`
98			`:i2_wb_dat_o: SOCM_PORT`
99			`defn: dat_o`
100			`len: 32`
101			`:i2_wb_ack_o: SOCM_PORT`
102			`defn: ack`
103			`len: 1`
104			`:i2_wb_err_o: SOCM_PORT`
105			`defn: err`
106			`len: 1`
107			`:i3: SOCM_IFC`
108			`name: wishbone_ma`
109			`dir: 1`
110			`version: "b3"`
111			`ports:`
112			`:i3_wb_cyc_i: SOCM_PORT`
113			`defn: cyc`
114			`len: 1`
115			`:i3_wb_stb_i: SOCM_PORT`
116			`defn: stb`
117			`len: 1`
118			`:i3_wb_adr_i: SOCM_PORT`
119			`defn: adr`
120			`len: 32`
121			`:i3_wb_sel_i: SOCM_PORT`
122			`defn: sel`
123			`len: 1`
124			`:i3_wb_we_i: SOCM_PORT`
125			`defn: we`
126			`len: 1`
127			`:i3_wb_dat_i: SOCM_PORT`
128			`defn: dat_i`
129			`len: 32`
130			`:i3_wb_dat_o: SOCM_PORT`
131			`defn: dat_o`
132			`len: 32`
133			`:i3_wb_ack_o: SOCM_PORT`
134			`defn: ack`
135			`len: 1`
136			`:i3_wb_err_o: SOCM_PORT`
137			`defn: err`
138			`len: 1`
139			`:i4: SOCM_IFC`
140			`name: wishbone_ma`
141			`dir: 1`
142			`version: "b3"`
143			`ports:`
144			`:i4_wb_cyc_i: SOCM_PORT`
145			`defn: cyc`
146			`len: 1`
147			`:i4_wb_stb_i: SOCM_PORT`
148			`defn: stb`
149			`len: 1`
150			`:i4_wb_adr_i: SOCM_PORT`
151			`defn: adr`
152			`len: 32`
153			`:i4_wb_sel_i: SOCM_PORT`
154			`defn: sel`
155			`len: 1`
156			`:i4_wb_we_i: SOCM_PORT`
157			`defn: we`
158			`len: 1`
159			`:i4_wb_dat_i: SOCM_PORT`
160			`defn: dat_i`
161			`len: 32`
162			`:i4_wb_dat_o: SOCM_PORT`
163			`defn: dat_o`
164			`len: 32`
165			`:i4_wb_ack_o: SOCM_PORT`
166			`defn: ack`
167			`len: 1`
168			`:i4_wb_err_o: SOCM_PORT`
169			`defn: err`
170			`len: 1`
171			`:i5: SOCM_IFC`
172			`name: wishbone_ma`
173			`dir: 1`
174			`version: "b3"`
175			`ports:`
176			`:i5_wb_cyc_i: SOCM_PORT`
177			`defn: cyc`
178			`len: 1`
179			`:i5_wb_stb_i: SOCM_PORT`
180			`defn: stb`
181			`len: 1`
182			`:i5_wb_adr_i: SOCM_PORT`
183			`defn: adr`
184			`len: 32`
185			`:i5_wb_sel_i: SOCM_PORT`
186			`defn: sel`
187			`len: 1`
188			`:i5_wb_we_i: SOCM_PORT`
189			`defn: we`
190			`len: 1`
191			`:i5_wb_dat_i: SOCM_PORT`
192			`defn: dat_i`
193			`len: 32`
194			`:i5_wb_dat_o: SOCM_PORT`
195			`defn: dat_o`
196			`len: 32`
197			`:i5_wb_ack_o: SOCM_PORT`
198			`defn: ack`
199			`len: 1`
200			`:i5_wb_err_o: SOCM_PORT`
201			`defn: err`
202			`len: 1`
203			`:i6: SOCM_IFC`
204			`name: wishbone_ma`
205			`dir: 1`
206			`version: "b3"`
207			`ports:`
208			`:i6_wb_cyc_i: SOCM_PORT`
209			`defn: cyc`
210			`len: 1`
211			`:i6_wb_stb_i: SOCM_PORT`
212			`defn: stb`
213			`len: 1`
214			`:i6_wb_adr_i: SOCM_PORT`
215			`defn: adr`
216			`len: 32`
217			`:i6_wb_sel_i: SOCM_PORT`
218			`defn: sel`
219			`len: 1`
220			`:i6_wb_we_i: SOCM_PORT`
221			`defn: we`
222			`len: 1`
223			`:i6_wb_dat_i: SOCM_PORT`
224			`defn: dat_i`
225			`len: 32`
226			`:i6_wb_dat_o: SOCM_PORT`
227			`defn: dat_o`
228			`len: 32`
229			`:i6_wb_ack_o: SOCM_PORT`
230			`defn: ack`
231			`len: 1`
232			`:i6_wb_err_o: SOCM_PORT`
233			`defn: err`
234			`len: 1`
235			`:i7: SOCM_IFC`
236			`name: wishbone_ma`
237			`dir: 1`
238			`version: "b3"`
239			`ports:`
240			`:i7_wb_cyc_i: SOCM_PORT`
241			`defn: cyc`
242			`len: 1`
243			`:i7_wb_stb_i: SOCM_PORT`
244			`defn: stb`
245			`len: 1`
246			`:i7_wb_adr_i: SOCM_PORT`
247			`defn: adr`
248			`len: 32`
249			`:i7_wb_sel_i: SOCM_PORT`
250			`defn: sel`
251			`len: 1`
252			`:i7_wb_we_i: SOCM_PORT`
253			`defn: we`
254			`len: 1`
255			`:i7_wb_dat_i: SOCM_PORT`
256			`defn: dat_i`
257			`len: 32`
258			`:i7_wb_dat_o: SOCM_PORT`
259			`defn: dat_o`
260			`len: 32`
261			`:i7_wb_ack_o: SOCM_PORT`
262			`defn: ack`
263			`len: 1`
264			`:i7_wb_err_o: SOCM_PORT`
265			`defn: err`
266			`len: 1`
267			`:t0: SOCM_IFC`
268			`name: wishbone_sl`
269			`dir: 1`
270			`version: "b3"`
271			`ports:`
272			`:t0_wb_cyc_o: SOCM_PORT`
273			`defn: cyc`
274			`len: 1`
275			`:t0_wb_stb_o: SOCM_PORT`
276			`defn: stb`
277			`len: 1`
278			`:t0_wb_adr_o: SOCM_PORT`
279			`defn: adr`
280			`len: 32`
281			`:t0_wb_sel_o: SOCM_PORT`
282			`defn: sel`
283			`len: 1`
284			`:t0_wb_we_o: SOCM_PORT`
285			`defn: we`
286			`len: 1`
287			`:t0_wb_dat_o: SOCM_PORT`
288			`defn: dat_i`
289			`len: 32`
290			`:t0_wb_dat_i: SOCM_PORT`
291			`defn: dat_i`
292			`len: 32`
293			`:t0_wb_ack_i: SOCM_PORT`
294			`defn: ack`
295			`len: 1`
296			`:t0_wb_err_i: SOCM_PORT`
297			`defn: err`
298			`len: 1`
299			`:t1: SOCM_IFC`
300			`name: wishbone_sl`
301			`dir: 1`
302			`version: "b3"`
303			`ports:`
304			`:t1_wb_cyc_o: SOCM_PORT`
305			`defn: cyc`
306			`len: 1`
307			`:t1_wb_stb_o: SOCM_PORT`
308			`defn: stb`
309			`len: 1`
310			`:t1_wb_adr_o: SOCM_PORT`
311			`defn: adr`
312			`len: 32`
313			`:t1_wb_sel_o: SOCM_PORT`
314			`defn: sel`
315			`len: 1`
316			`:t1_wb_we_o: SOCM_PORT`
317			`defn: we`
318			`len: 1`
319			`:t1_wb_dat_o: SOCM_PORT`
320			`defn: dat_i`
321			`len: 32`
322			`:t1_wb_dat_i: SOCM_PORT`
323			`defn: dat_i`
324			`len: 32`
325			`:t1_wb_ack_i: SOCM_PORT`
326			`defn: ack`
327			`len: 1`
328			`:t1_wb_err_i: SOCM_PORT`
329			`defn: err`
330			`len: 1`
331			`:t2: SOCM_IFC`
332			`name: wishbone_sl`
333			`dir: 1`
334			`version: "b3"`
335			`ports:`
336			`:t2_wb_cyc_o: SOCM_PORT`
337			`defn: cyc`
338			`len: 1`
339			`:t2_wb_stb_o: SOCM_PORT`
340			`defn: stb`
341			`len: 1`
342			`:t2_wb_adr_o: SOCM_PORT`
343			`defn: adr`
344			`len: 32`
345			`:t2_wb_sel_o: SOCM_PORT`
346			`defn: sel`
347			`len: 1`
348			`:t2_wb_we_o: SOCM_PORT`
349			`defn: we`
350			`len: 1`
351			`:t2_wb_dat_o: SOCM_PORT`
352			`defn: dat_i`
353			`len: 32`
354			`:t2_wb_dat_i: SOCM_PORT`
355			`defn: dat_i`
356			`len: 32`
357			`:t2_wb_ack_i: SOCM_PORT`
358			`defn: ack`
359			`len: 1`
360			`:t2_wb_err_i: SOCM_PORT`
361			`defn: err`
362			`len: 1`
363			`:t3: SOCM_IFC`
364			`name: wishbone_sl`
365			`dir: 1`
366			`version: "b3"`
367			`ports:`
368			`:t3_wb_cyc_o: SOCM_PORT`
369			`defn: cyc`
370			`len: 1`
371			`:t3_wb_stb_o: SOCM_PORT`
372			`defn: stb`
373			`len: 1`
374			`:t3_wb_adr_o: SOCM_PORT`
375			`defn: adr`
376			`len: 32`
377			`:t3_wb_sel_o: SOCM_PORT`
378			`defn: sel`
379			`len: 1`
380			`:t3_wb_we_o: SOCM_PORT`
381			`defn: we`
382			`len: 1`
383			`:t3_wb_dat_o: SOCM_PORT`
384			`defn: dat_i`
385			`len: 32`
386			`:t3_wb_dat_i: SOCM_PORT`
387			`defn: dat_i`
388			`len: 32`
389			`:t3_wb_ack_i: SOCM_PORT`
390			`defn: ack`
391			`len: 1`
392			`:t3_wb_err_i: SOCM_PORT`
393			`defn: err`
394			`len: 1`
395			`:t4: SOCM_IFC`
396			`name: wishbone_sl`
397			`dir: 1`
398			`version: "b3"`
399			`ports:`
400			`:t4_wb_cyc_o: SOCM_PORT`
401			`defn: cyc`
402			`len: 1`
403			`:t4_wb_stb_o: SOCM_PORT`
404			`defn: stb`
405			`len: 1`
406			`:t4_wb_adr_o: SOCM_PORT`
407			`defn: adr`
408			`len: 32`
409			`:t4_wb_sel_o: SOCM_PORT`
410			`defn: sel`
411			`len: 1`
412			`:t4_wb_we_o: SOCM_PORT`
413			`defn: we`
414			`len: 1`
415			`:t4_wb_dat_o: SOCM_PORT`
416			`defn: dat_i`
417			`len: 32`
418			`:t4_wb_dat_i: SOCM_PORT`
419			`defn: dat_i`
420			`len: 32`
421			`:t4_wb_ack_i: SOCM_PORT`
422			`defn: ack`
423			`len: 1`
424			`:t4_wb_err_i: SOCM_PORT`
425			`defn: err`
426			`len: 1`
427			`:t5: SOCM_IFC`
428			`name: wishbone_sl`
429			`dir: 1`
430			`version: "b3"`
431			`ports:`
432			`:t5_wb_cyc_o: SOCM_PORT`
433			`defn: cyc`
434			`len: 1`
435			`:t5_wb_stb_o: SOCM_PORT`
436			`defn: stb`
437			`len: 1`
438			`:t5_wb_adr_o: SOCM_PORT`
439			`defn: adr`
440			`len: 32`
441			`:t5_wb_sel_o: SOCM_PORT`
442			`defn: sel`
443			`len: 1`
444			`:t5_wb_we_o: SOCM_PORT`
445			`defn: we`
446			`len: 1`
447			`:t5_wb_dat_o: SOCM_PORT`
448			`defn: dat_i`
449			`len: 32`
450			`:t5_wb_dat_i: SOCM_PORT`
451			`defn: dat_i`
452			`len: 32`
453			`:t5_wb_ack_i: SOCM_PORT`
454			`defn: ack`
455			`len: 1`
456			`:t5_wb_err_i: SOCM_PORT`
457			`defn: err`
458			`len: 1`
459			`:t6: SOCM_IFC`
460			`name: wishbone_sl`
461			`dir: 1`
462			`version: "b3"`
463			`ports:`
464			`:t6_wb_cyc_o: SOCM_PORT`
465			`defn: cyc`
466			`len: 1`
467			`:t6_wb_stb_o: SOCM_PORT`
468			`defn: stb`
469			`len: 1`
470			`:t6_wb_adr_o: SOCM_PORT`
471			`defn: adr`
472			`len: 32`
473			`:t6_wb_sel_o: SOCM_PORT`
474			`defn: sel`
475			`len: 1`
476			`:t6_wb_we_o: SOCM_PORT`
477			`defn: we`
478			`len: 1`
479			`:t6_wb_dat_o: SOCM_PORT`
480			`defn: dat_i`
481			`len: 32`
482			`:t6_wb_dat_i: SOCM_PORT`
483			`defn: dat_i`
484			`len: 32`
485			`:t6_wb_ack_i: SOCM_PORT`
486			`defn: ack`
487			`len: 1`
488			`:t6_wb_err_i: SOCM_PORT`
489			`defn: err`
490			`len: 1`
491			`:t7: SOCM_IFC`
492			`name: wishbone_sl`
493			`dir: 1`
494			`version: "b3"`
495			`ports:`
496			`:t7_wb_cyc_o: SOCM_PORT`
497			`defn: cyc`
498			`len: 1`
499			`:t7_wb_stb_o: SOCM_PORT`
500			`defn: stb`

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