OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Makefile] - Blame information for rev 56

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 jt_eaton
SHELL=/bin/sh
2
MAKE=make
3
CUR_DIR=$(shell pwd)
4 56 jt_eaton
home=$(CUR_DIR)
5 6 jt_eaton
design=socgen
6
 
7
 
8
all: run_sims build_fpgas check_sims check_fpgas
9
 
10 56 jt_eaton
.PHONY build_soc:
11
build_soc:
12 10 jt_eaton
        (\
13 56 jt_eaton
        rm -r work  ;\
14
        soc_link   ;\
15
        soc_builder;\
16
         )
17 6 jt_eaton
 
18
 
19
 
20
.PHONY build_sw:
21 56 jt_eaton
build_sw: build_soc
22 49 jt_eaton
        @for PROJECT in `ls $(CUR_DIR)/work`; do \
23 6 jt_eaton
        echo "################################################"; \
24
        echo "build_sw: $$PROJECT ####"; echo; \
25 56 jt_eaton
        cd ${home}/work/$$PROJECT/bin;\
26 6 jt_eaton
        ${MAKE} group_build_sw;\
27
        done; \
28
 
29
.PHONY run_sims:
30
run_sims: build_sw
31 49 jt_eaton
        @for PROJECT in `ls $(CUR_DIR)/work`; do \
32 6 jt_eaton
        echo "################################################"; \
33
        echo "run_sims: $$PROJECT ####"; echo; \
34 56 jt_eaton
        cd ${home}/work/$$PROJECT/bin;\
35 6 jt_eaton
        ${MAKE} group_run_sims;\
36
        done; \
37
 
38
.PHONY build_fpgas:
39
build_fpgas:
40 49 jt_eaton
        @for PROJECT in `ls $(CUR_DIR)/work`; do \
41 6 jt_eaton
        echo "################################################"; \
42
        echo "build_fpgas: $$PROJECT ####"; echo; \
43 56 jt_eaton
        cd ${home}/work/$$PROJECT/bin;\
44 6 jt_eaton
        ${MAKE} group_build_fpgas;\
45
        done; \
46
 
47 49 jt_eaton
 
48
 
49
 
50
 
51 6 jt_eaton
.PHONY check_sims:
52 49 jt_eaton
check_sims:
53
        @for COMP in `ls $(CUR_DIR)/work`; do \
54 54 jt_eaton
        echo "*******************************************************************************************";\
55 49 jt_eaton
        echo " number of $$COMP sims run";\
56 54 jt_eaton
        find ./work/$$COMP  | grep dut| grep -v children| grep -v cov | wc -l;\
57 6 jt_eaton
        echo " number of sims that finished";\
58 54 jt_eaton
        find ./work/$$COMP  | grep _sim.log | xargs grep PASSED $1    | wc -l ;\
59 6 jt_eaton
        echo " number of warnings";\
60 54 jt_eaton
        find ./work/$$COMP  | grep _sim.log | xargs grep WARNING $1   | wc -l ;\
61 6 jt_eaton
        echo " number of errors";\
62 54 jt_eaton
        find ./work/$$COMP  | grep _sim.log | xargs grep ERROR $1     | wc -l ;\
63 49 jt_eaton
        echo " Code Coverage";\
64 19 jt_eaton
        echo " number of warnings";\
65 54 jt_eaton
        find ./work/$$COMP  | grep _cov.log | xargs grep WARNING $1  ;\
66 19 jt_eaton
        echo " number of errors";\
67 54 jt_eaton
        find ./work/$$COMP  | grep _cov.log | xargs grep ERROR $1    ;\
68 49 jt_eaton
        done;
69 6 jt_eaton
 
70
 
71
.PHONY check_fpgas:
72
check_fpgas:
73
        (\
74 56 jt_eaton
        cd ${home}/work  ;\
75 6 jt_eaton
        echo " number of fpgas";\
76 54 jt_eaton
        find . | grep def_file | grep -v children | grep -v .svn | wc -l   ;\
77 6 jt_eaton
        echo " number that finished";\
78 54 jt_eaton
        find . | grep Board_Design_jtag.bit | wc -l ;\
79 6 jt_eaton
         )
80
 
81
 
82
 
83
 
84
 
85
 
86
 
87
 
88
 
89
 
90
 
91
 
92
 
93
 
94
 
95
 
96
 
97
 
98
 
99
 
100
 
101
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.