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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
digilentinc.com
Nexys2
jtag
tap  default
 
 
 
 
 
 

 
 
   
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSource
        include
      
 
 
      
        dest_dir
        ../verilog/syn/
        verilogSource
        libraryDir
      
 
 
 
 
 
 
   
 

 
 
 
 
 
 
 
 
 
 
 

       
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
      
 
 
 
 
 
 

 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`digilentinc.com`
38			`Nexys2`
39			`jtag`
40			`tap default`
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51			`fs-syn`
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55			`../verilog/copyright.v`
56			`verilogSource`
57			`include`
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62			`dest_dir`
63			`../verilog/syn/`
64			`verilogSource`
65			`libraryDir`
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91			`syn:Synthesis:`
92
93			`Verilog`
94
95
96			`fs-syn`
97
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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [jtag/] [rtl/] [xml/] [cde_jtag_tap.xml] - Blame information for rev 131