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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [verilog/] [sram_def.v] - Blame information for rev 134

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1 131 jt_eaton 
/**********************************************************************/
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/*                                                                    */
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/*                                                                    */
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/*   Copyright (c) 2012 Ouabache Design Works                         */
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/*                                                                    */
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/*          All Rights Reserved Worldwide                             */
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/*                                                                    */
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/*   Licensed under the Apache License,Version2.0 (the'License');     */
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/*   you may not use this file except in compliance with the License. */
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/*   You may obtain a copy of the License at                          */
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/*                                                                    */
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/*       http://www.apache.org/licenses/LICENSE-2.0                   */
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/*                                                                    */
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/*   Unless required by applicable law or agreed to in                */
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/*   writing, software distributed under the License is               */
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/*   distributed on an 'AS IS' BASIS, WITHOUT WARRANTIES              */
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/*   OR CONDITIONS OF ANY KIND, either express or implied.            */
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/*   See the License for the specific language governing              */
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/*   permissions and limitations under the License.                   */
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/**********************************************************************/
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 module
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  cde_sram_def
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    #( parameter
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      ADDR=10,
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      WIDTH=8,
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      WORDS=1024,
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      WRITETHRU=0,
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      INIT_FILE="NONE",
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      MEM="NONE",
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      INSTANCE_NAME="../../../../../children/")
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     (
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 input   wire                 clk,
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 input   wire                 cs,
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 input   wire                 rd,
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 input   wire                 wr,
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 input   wire    [ ADDR-1 :  0]        addr,
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 input   wire    [ WIDTH-1 :  0]        wdata,
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 output   reg    [ WIDTH-1 :  0]        rdata);
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// Memory Array
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reg [WIDTH-1:0] mem[0:WORDS-1];
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// If used as Rom then load a memory image at startup
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initial
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  begin
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   if( MEM  == "NONE")
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     begin
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     end
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   else
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        begin
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        $readmemh(MEM, mem);
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        end
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  end
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// Write function
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// Write function
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always@(posedge clk)
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        if( wr && cs ) mem[addr[ADDR-1:0]] <= wdata[WIDTH-1:0];
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generate
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if( WRITETHRU)
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  begin
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  // Read function gets new data if also a write cycle
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  // latch the read addr for next cycle
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  reg   [ADDR-1:0]          l_raddr;
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  reg                       l_cycle;
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  always@(posedge clk)
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        l_cycle    <=  rd && cs  ;
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  always@(posedge clk)      l_raddr    <= addr;
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  // Read into a wire and then pass to rdata because some synth tools can't handle a memory in a always block
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  wire  [WIDTH-1:0] tmp_rdata;
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  assign                    tmp_rdata  =      (l_cycle )?mem[{l_raddr[ADDR-1:0]}]:{WIDTH{1'b1}};
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  always@(*)                rdata  =      tmp_rdata;
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  end
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else
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  begin
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  // Read function gets old data if also a write cycle
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  always@(posedge clk)
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        if( rd && cs ) rdata             <= mem[{addr[ADDR-1:0]}];
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        else           rdata             <= {WIDTH{1'b1}};
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  end
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endgenerate
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  endmodule

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