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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_be.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://digilentinc.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
digilentinc.com
Nexys2
sram
be  default
 
 
 

 
 
 
 
 
 

 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
  
 
 
   
      fs-syn
 
      
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-lint
 
 
      
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
   
 
 
 

 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
 
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
 
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
 
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
 
      
 
 
 

ADDR10
WIDTH8
WORDS1024
WRITETHRU0

 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
be
wire
in

 
 
 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://digilentinc.com"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`digilentinc.com`
13			`Nexys2`
14			`sram`
15			`be default`
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34			`fs-sim`
35
36
37			`dest_dir../verilog/`
38			`verilogSourcelibraryDir`
39
40
41
42
43
44
45			`fs-syn`
46
47
48			`dest_dir../verilog/`
49			`verilogSourcelibraryDir`
50
51
52
53
54
55
56
57
58			`fs-lint`
59
60
61
62			`dest_dir../verilog/lint/`
63			`verilogSourcelibraryDir`
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82			`sim:Simulation:`
83
84			`Verilog`
85
86
87			`fs-sim`
88
89
90
91
92			`syn:Synthesis:`
93
94			`Verilog`
95
96
97			`fs-syn`
98
99
100
101
102
103			`lintlint`
104
105			`Verilog`
106
107
108			`fs-lint`
109
110
111
112
113
114
115
116
117
118
119
120
121
122			`ADDR10`
123			`WIDTH8`
124			`WORDS1024`
125			`WRITETHRU0`
126
127
128
129
130			`clk`
131			`wire`
132			`in`
133
134
135			`cs`
136			`wire`
137			`in`
138
139
140			`wr`
141			`wire`
142			`in`
143
144
145			`rd`
146			`wire`
147			`in`
148
149
150			`be`
151			`wire`
152			`in`
153
154
155
156
157
158			`addr`
159			`wire`
160			`in`
161			`ADDR-10`
162
163
164
165			`wdata`
166			`wire`
167			`in`
168			`WIDTH-10`
169
170
171			`rdata`
172			`reg`
173			`out`
174			`WIDTH-10`
175
176
177
178
179
180
181
182
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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_be.xml] - Blame information for rev 134