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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://digilentinc.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
digilentinc.com
Nexys2
sram
def  default
 

 
 
 
 

 
 
 

 
 
 
 
   
      fs-sim
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
   
      fs-lint
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 
 

       
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-syn
                     
              
 
 
              
              lintlint
              Verilog
              
                     
                            fs-lint
                     
              
 
 
 
 
 
 
 
 
      
 
 
 

ADDR10
WIDTH8
WORDS1024
WRITETHRU0

 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
addr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


Line No.	Rev	Author	Line
1	131	jt_eaton
2
5
6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://digilentinc.com"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`digilentinc.com`
13			`Nexys2`
14			`sram`
15			`def default`
16
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22
23
24
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31
32			`fs-sim`
33
34
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37			`dest_dir../verilog/`
38			`verilogSourcelibraryDir`
39
40
41
42
43
44
45
46
47			`fs-syn`
48
49
50
51
52			`dest_dir../verilog/`
53			`verilogSourcelibraryDir`
54
55
56
57
58
59
60
61
62
63
64			`fs-lint`
65
66
67
68			`dest_dir../verilog/lint/`
69			`verilogSourcelibraryDir`
70
71
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75
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92			`sim:Simulation:`
93			`Verilog`
94
95
96			`fs-sim`
97
98
99
100
101			`syn:Synthesis:`
102			`Verilog`
103
104
105			`fs-syn`
106
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109
110
111			`lintlint`
112			`Verilog`
113
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115			`fs-lint`
116
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123
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130
131			`ADDR10`
132			`WIDTH8`
133			`WORDS1024`
134			`WRITETHRU0`
135
136
137
138
139			`clk`
140			`wire`
141			`in`
142
143
144			`cs`
145			`wire`
146			`in`
147
148
149			`wr`
150			`wire`
151			`in`
152
153
154			`rd`
155			`wire`
156			`in`
157
158
159
160			`addr`
161			`wire`
162			`in`
163			`ADDR-10`
164
165
166
167			`wdata`
168			`wire`
169			`in`
170			`WIDTH-10`
171
172
173			`rdata`
174			`reg`
175			`out`
176			`WIDTH-10`
177
178
179
180
181
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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_def.xml] - Blame information for rev 134