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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://digilentinc.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
digilentinc.com
Nexys2
sram
dp  default
 
 

 
 
 
 
 
 

 
 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
   
      fs-lint
 
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

       
 
 
              
              sim:*Simulation:*
              Verilog
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
                     
                            fs-syn
                     
              
 
              
              lintlint
              Verilog
                     
                            fs-lint
                     
              
 
 
 
 
 
 
 
 
      
 
 
 

 
ADDR10
WIDTH8
WORDS1024
WRITETHRU0
DEFAULT{WIDTH{1'b1}}

 
 
 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
waddr
wire
in
ADDR-10

 
raddr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
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6			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
7			`xmlns:socgen="http://digilentinc.com"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
10			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
11
12			`digilentinc.com`
13			`Nexys2`
14			`sram`
15			`dp default`
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34			`fs-sim`
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37			`dest_dir../verilog/`
38			`verilogSourcelibraryDir`
39
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45
46
47			`fs-syn`
48
49
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51			`dest_dir../verilog/`
52			`verilogSourcelibraryDir`
53
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63			`fs-lint`
64
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68			`dest_dir../verilog/lint/`
69			`verilogSourcelibraryDir`
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95			`sim:Simulation:`
96			`Verilog`
97
98			`fs-sim`
99
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103			`syn:Synthesis:`
104			`Verilog`
105
106			`fs-syn`
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111			`lintlint`
112			`Verilog`
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114			`fs-lint`
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131			`ADDR10`
132			`WIDTH8`
133			`WORDS1024`
134			`WRITETHRU0`
135			`DEFAULT{WIDTH{1'b1}}`
136
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142			`clk`
143			`wire`
144			`in`
145
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147			`cs`
148			`wire`
149			`in`
150
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152			`wr`
153			`wire`
154			`in`
155
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157			`rd`
158			`wire`
159			`in`
160
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163			`waddr`
164			`wire`
165			`in`
166			`ADDR-10`
167
168
169			`raddr`
170			`wire`
171			`in`
172			`ADDR-10`
173
174
175
176			`wdata`
177			`wire`
178			`in`
179			`WIDTH-10`
180
181
182			`rdata`
183			`reg`
184			`out`
185			`WIDTH-10`
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