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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://digilentinc.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
digilentinc.com
Nexys2
sram
dp
 
 

 
 
 
 
 
 

 
 
 

 
 
 
   
      fs-sim
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
 
  
 
 
   
      fs-syn
 
 
       
        dest_dir../verilog/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
   
      fs-lint
 
 
 
       
        dest_dir../verilog/lint/
        verilogSourcelibraryDir
      
 
 
   
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

 
 
                
                        
                                verilog
                                verilog
                                cde_sram_dp
                                
                                        
                                                ADDR
                                                8
                                        
                                        
                                                WIDTH
                                                8
                                        
                                        
                                                WORDS
                                                256
                                        
                                        
                                                WRITETHRU
                                                1
                                        
                                
                                
                                        fs-sim
                                
                        
                
 
 
 
       
 
 
        
        rtl
        verilog:Kactus2:
        verilog
        
 
              
              sim:*Simulation:*
              Verilog
                     
                            fs-sim
                     
              
 
              
              syn:*Synthesis:*
              Verilog
                     
                            fs-syn
                     
              
 
              
              lint:*Lint:*
              Verilog
                     
                            fs-lint
                     
              
 
 
 
 
 
 
 
 
      
 
 
 

 
ADDR10
WIDTH8
WORDS1024
WRITETHRU0

 
 
 

 
clk
wire
in

 
cs
wire
in

 
wr
wire
in

 
rd
wire
in

 
 
waddr
wire
in
ADDR-10

 
raddr
wire
in
ADDR-10

 
 
wdata
wire
in
WIDTH-10

 
rdata
reg
out
WIDTH-10

 
 
 

 

 
 
 
 
 
 
 
 
 
 
 


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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [Nexys2/] [ip/] [sram/] [rtl/] [xml/] [sram_dp.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	131	jt_eaton
2
5	135	jt_eaton
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7	131	jt_eaton	`xmlns:socgen="http://digilentinc.com"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
9	135	jt_eaton	`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
10			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
11	131	jt_eaton
12	135	jt_eaton	`digilentinc.com`
13			`Nexys2`
14			`sram`
15			`dp`
16	131	jt_eaton
17
18	135	jt_eaton
19	131	jt_eaton
20
21
22
23
24
25	135	jt_eaton
26	131	jt_eaton
27
28
29	135	jt_eaton
30	131	jt_eaton
31
32
33	135	jt_eaton
34			`fs-sim`
35	131	jt_eaton
36	135	jt_eaton
37			`dest_dir../verilog/`
38			`verilogSourcelibraryDir`
39
40	131	jt_eaton
41
42
43	135	jt_eaton
44	131	jt_eaton
45
46	135	jt_eaton
47			`fs-syn`
48	131	jt_eaton
49
50	135	jt_eaton
51			`dest_dir../verilog/`
52			`verilogSourcelibraryDir`
53
54	131	jt_eaton
55
56	135	jt_eaton
57	131	jt_eaton
58
59
60
61
62	135	jt_eaton
63			`fs-lint`
64	131	jt_eaton
65
66
67	135	jt_eaton
68			`dest_dir../verilog/lint/`
69			`verilogSourcelibraryDir`
70
71	131	jt_eaton
72
73	135	jt_eaton
74	131	jt_eaton
75
76
77
78
79
80
81
82
83	135	jt_eaton
84	131	jt_eaton
85
86
87
88
89
90	135	jt_eaton
91	131	jt_eaton
92
93	135	jt_eaton
94
95			`verilog`
96			`verilog`
97			`cde_sram_dp`
98
99
100			`ADDR`
101			`8`
102
103
104			`WIDTH`
105			`8`
106
107
108			`WORDS`
109			`256`
110
111
112			`WRITETHRU`
113			`1`
114
115
116
117			`fs-sim`
118
119
120
121	131	jt_eaton
122	135	jt_eaton
123
124
125	131	jt_eaton
126
127	135	jt_eaton
128			`rtl`
129			`verilog:Kactus2:`
130			`verilog`
131
132	131	jt_eaton
133	135	jt_eaton
134			`sim:Simulation:`
135			`Verilog`
136
137			`fs-sim`
138
139
140	131	jt_eaton
141	135	jt_eaton
142			`syn:Synthesis:`
143			`Verilog`
144
145			`fs-syn`
146
147
148	131	jt_eaton
149	135	jt_eaton
150			`lint:Lint:`
151			`Verilog`
152
153			`fs-lint`
154
155
156
157
158
159
160	131	jt_eaton
161
162
163
164	135	jt_eaton
165	131	jt_eaton
166
167
168	135	jt_eaton
169	131	jt_eaton
170	135	jt_eaton	`ADDR10`
171			`WIDTH8`
172			`WORDS1024`
173			`WRITETHRU0`
174
175	131	jt_eaton
176
177
178	135	jt_eaton
179	131	jt_eaton
180	135	jt_eaton	`clk`
181			`wire`
182			`in`
183
184	131	jt_eaton
185	135	jt_eaton	`cs`
186			`wire`
187			`in`
188
189	131	jt_eaton
190	135	jt_eaton	`wr`
191			`wire`
192			`in`
193
194	131	jt_eaton
195	135	jt_eaton	`rd`
196			`wire`
197			`in`
198
199	131	jt_eaton
200
201	135	jt_eaton	`waddr`
202			`wire`
203			`in`
204			`ADDR-10`
205
206	131	jt_eaton
207	135	jt_eaton	`raddr`
208			`wire`
209			`in`
210			`ADDR-10`
211
212	131	jt_eaton
213
214	135	jt_eaton	`wdata`
215			`wire`
216			`in`
217			`WIDTH-10`
218
219	131	jt_eaton
220	135	jt_eaton	`rdata`
221			`reg`
222			`out`
223			`WIDTH-10`
224
225	131	jt_eaton
226
227
228	135	jt_eaton
229	131	jt_eaton
230	135	jt_eaton
231	131	jt_eaton
232
233
234
235
236
237
238
239
240
241
242	135	jt_eaton