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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [componentCfg.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
 
digilentinc.com
nexys2
iceskate
 
 
2
_
_
_
VARIANT
 

  
   TestBenches
   sim
   testbenches
   testbench
   version
  
  
   Fpgas
   syn
   ise
   chip
   variant
  

 
 
 

 
/doc
 

 
 

 
 
 

 
 
 
 

 
 
       
         default
         default
         default_tb
         default_lint
         
         CLOCK_FREQ50
         CLOCK_PLL_MULT2
         CLOCK_PLL_DIV4
         CLOCK_PLL_SIZE4
         CLOCK_SRC0
         RESET_SENSE1
         JTAG_USER1_WIDTH8
         JTAG_USER1_RESET8'h12
         JTAG_USER2_WIDTH8
         JTAG_USER2_RESET8'h78
 
         
       
 
 
 
 
       
         core
         core
         
         JTAG_USER1_WIDTH8
         JTAG_USER1_RESET8'h00
         JTAG_USER2_WIDTH8
         JTAG_USER2_RESET8'h00
 
         
       
 
 
 
 
 
 
       
         rot
         rot
         
         CLOCK_FREQ50
         CLOCK_PLL_MULT2
         CLOCK_PLL_DIV4
         CLOCK_PLL_SIZE4
         CLOCK_SRC0
         RESET_SENSE1
         JTAG_USER1_WIDTH8
         JTAG_USER1_RESET8'h12
         JTAG_USER2_WIDTH8
         JTAG_USER2_RESET8'h78
         
       
 
 
 
 
 
 
 
 
 

 

 
iceskate/sim
 
 
 
 

 
 
 

iceskate_default_tb
default
default_tb

    PERIOD40
    TIMEOUT100000


  
  iceskate_core  TB.test.dut.core
  


  icarus
  coverage


 
 

iceskate_default_lint
default
default_lint

  rtl_check

 

 
 
 
 

 
 
 
 

      
        default
        default
        iceskate_default_lint
      

 
 
 
 
 
 
 

 
 
      
        default
        rot
        iceskate_default_tb
        
           PERIOD20
           TIMEOUT800000
        
      
 
 
 

 
 

 
 
 
 
 

 
 
iceskate/syn
 
 
 
 
 
 
 

 
 
 

iceskate_rot
rot
default

ise

    digilentinc.com
    Nexys2
    fpga
    xc3s1200e-fg320-5


 
 
 
 
 
 

 
 
 
 
 
 
 
 

 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [componentCfg.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
5
6			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
7			`xmlns:socgen="http://opencores.org"`
8			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">`
9
10			`digilentinc.com`
11			`nexys2`
12			`iceskate`
13
14
15			`2`
16			`_`
17			`_`
18			`_`
19			`VARIANT`
20
21
22
23			`TestBenches`
24			`sim`
25			`testbenches`
26			`testbench`
27			`version`
28
29
30			`Fpgas`
31			`syn`
32			`ise`
33			`chip`
34			`variant`
35
36
37
38
39
40
41
42			`/doc`
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60			`default`
61			`default`
62			`default_tb`
63			`default_lint`
64
65			`CLOCK_FREQ50`
66			`CLOCK_PLL_MULT2`
67			`CLOCK_PLL_DIV4`
68			`CLOCK_PLL_SIZE4`
69			`CLOCK_SRC0`
70			`RESET_SENSE1`
71			`JTAG_USER1_WIDTH8`
72			`JTAG_USER1_RESET8'h12`
73			`JTAG_USER2_WIDTH8`
74			`JTAG_USER2_RESET8'h78`
75
76
77
78
79
80
81
82
83			`core`
84			`core`
85
86			`JTAG_USER1_WIDTH8`
87			`JTAG_USER1_RESET8'h00`
88			`JTAG_USER2_WIDTH8`
89			`JTAG_USER2_RESET8'h00`
90
91
92
93
94
95
96
97
98
99
100			`rot`
101			`rot`
102
103			`CLOCK_FREQ50`
104			`CLOCK_PLL_MULT2`
105			`CLOCK_PLL_DIV4`
106			`CLOCK_PLL_SIZE4`
107			`CLOCK_SRC0`
108			`RESET_SENSE1`
109			`JTAG_USER1_WIDTH8`
110			`JTAG_USER1_RESET8'h12`
111			`JTAG_USER2_WIDTH8`
112			`JTAG_USER2_RESET8'h78`
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128			`iceskate/sim`
129
130
131
132
133
134
135
136
137
138			`iceskate_default_tb`
139			`default`
140			`default_tb`
141
142			`PERIOD40`
143			`TIMEOUT100000`
144
145
146
147			`iceskate_core TB.test.dut.core`
148
149
150
151			`icarus`
152			`coverage`
153
154
155
156
157
158			`iceskate_default_lint`
159			`default`
160			`default_lint`
161
162			`rtl_check`
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177			`default`
178			`default`
179			`iceskate_default_lint`
180
181
182
183
184
185
186
187
188
189
190
191
192
193			`default`
194			`rot`
195			`iceskate_default_tb`
196
197			`PERIOD20`
198			`TIMEOUT800000`
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216			`iceskate/syn`
217
218
219
220
221
222
223
224
225
226
227
228
229			`iceskate_rot`
230			`rot`
231			`default`
232
233			`ise`
234
235			`digilentinc.com`
236			`Nexys2`
237			`fpga`
238			`xc3s1200e-fg320-5`
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
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