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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [rtl/] [verilog/] [top] - Blame information for rev 135

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reg [31:0] COUNTER;
 
always@(posedge clk)
begin
               COUNTER <= COUNTER + 32'h00000001;
end
 
 
 
 
assign jtag_tdo = 1'b0;
 
 
assign PosD = COUNTER[29:14];
 
 
 
 
assign   PosL[0]    = PosS[0];
assign   PosL[1]    = PosS[1];
assign   PosL[2]    = PosS[2];
assign   PosL[3]    = PosS[3];
assign   PosL[4]    = COUNTER[18];
assign   PosL[5]    = COUNTER[19];
assign   PosL[6]    = PosB[0];
assign   PosL[7]    = reset;
 
 
 
assign    eppdb_pad_out            =    8'h00;
assign    flashcs_n_pad_out        =    1'b1;
assign    flashrp_pad_out          =    1'b0;
assign    ja_1_pad_out             =    1'b0;
assign    ja_10_pad_out            =    1'b0;
assign    ja_2_pad_out             =    1'b0;
assign    ja_3_pad_out             =    1'b0;
assign    ja_4_pad_out             =    1'b0;
assign    ja_7_pad_out             =    1'b0;
assign    ja_8_pad_out             =    1'b0;
assign    ja_9_pad_out             =    1'b0;
assign    jb_1_pad_out             =    1'b0;
assign    jb_10_pad_out            =    1'b0;
assign    jb_2_pad_out             =    1'b0;
assign    jb_3_pad_out             =    1'b0;
assign    jb_4_pad_out             =    1'b0;
assign    jb_7_pad_out             =    1'b0;
assign    jb_8_pad_out             =    1'b0;
assign    jb_9_pad_out             =    1'b0;
assign    jc_1_pad_out             =    1'b0;
assign    jc_10_pad_out            =    1'b0;
assign    jc_2_pad_out             =    1'b0;
assign    jc_3_pad_out             =    1'b0;
assign    jc_4_pad_out             =    1'b0;
assign    jc_7_pad_out             =    1'b0;
assign    jc_8_pad_out             =    1'b0;
assign    jc_9_pad_out             =    1'b0;
 
assign    memadr_pad_out           =    23'b0;
assign    memdb_pad_out            =    16'b0;
assign    memoe_pad_out            =    1'b0;
assign    memwr_n_pad_out          =    1'b1;
assign    pio_pad_out              =    40'b0;
assign    ps2_clk_pad_out          =    1'b0;
assign    ps2_data_pad_out         =    1'b0;
assign    ramadv_n_pad_out         =    1'b1;
assign    ramclk_pad_out           =    1'b0;
assign    ramcre_pad_out           =    1'b0;
assign    ramcs_pad_out            =    1'b0;
assign    ramlb_n_pad_out          =    1'b1;
assign    ramub_n_pad_out          =    1'b1;
assign    rs_tx_pad_out            =    1'b1;
assign    rts_pad_out              =    1'b0;
assign    txd_pad_out              =    1'b1;
assign    usbrdy_pad_out           =    1'b0;
assign    vga_blue_pad_out         =    2'b00;
assign    vga_green_pad_out        =    3'b000;
assign    vga_hsync_n_pad_out      =    1'b1;
assign    vga_red_pad_out          =    3'b000;
assign    vga_vsync_n_pad_out      =    1'b1;
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
3
4			`reg [31:0] COUNTER;`
5
6			`always@(posedge clk)`
7			`begin`
8			`COUNTER <= COUNTER + 32'h00000001;`
9			`end`
10
11
12
13
14			`assign jtag_tdo = 1'b0;`
15
16
17			`assign PosD = COUNTER[29:14];`
18
19
20
21
22			`assign PosL[0] = PosS[0];`
23			`assign PosL[1] = PosS[1];`
24			`assign PosL[2] = PosS[2];`
25			`assign PosL[3] = PosS[3];`
26			`assign PosL[4] = COUNTER[18];`
27			`assign PosL[5] = COUNTER[19];`
28			`assign PosL[6] = PosB[0];`
29			`assign PosL[7] = reset;`
30
31
32
33			`assign eppdb_pad_out = 8'h00;`
34			`assign flashcs_n_pad_out = 1'b1;`
35			`assign flashrp_pad_out = 1'b0;`
36			`assign ja_1_pad_out = 1'b0;`
37			`assign ja_10_pad_out = 1'b0;`
38			`assign ja_2_pad_out = 1'b0;`
39			`assign ja_3_pad_out = 1'b0;`
40			`assign ja_4_pad_out = 1'b0;`
41			`assign ja_7_pad_out = 1'b0;`
42			`assign ja_8_pad_out = 1'b0;`
43			`assign ja_9_pad_out = 1'b0;`
44			`assign jb_1_pad_out = 1'b0;`
45			`assign jb_10_pad_out = 1'b0;`
46			`assign jb_2_pad_out = 1'b0;`
47			`assign jb_3_pad_out = 1'b0;`
48			`assign jb_4_pad_out = 1'b0;`
49			`assign jb_7_pad_out = 1'b0;`
50			`assign jb_8_pad_out = 1'b0;`
51			`assign jb_9_pad_out = 1'b0;`
52			`assign jc_1_pad_out = 1'b0;`
53			`assign jc_10_pad_out = 1'b0;`
54			`assign jc_2_pad_out = 1'b0;`
55			`assign jc_3_pad_out = 1'b0;`
56			`assign jc_4_pad_out = 1'b0;`
57			`assign jc_7_pad_out = 1'b0;`
58			`assign jc_8_pad_out = 1'b0;`
59			`assign jc_9_pad_out = 1'b0;`
60
61			`assign memadr_pad_out = 23'b0;`
62			`assign memdb_pad_out = 16'b0;`
63			`assign memoe_pad_out = 1'b0;`
64			`assign memwr_n_pad_out = 1'b1;`
65			`assign pio_pad_out = 40'b0;`
66			`assign ps2_clk_pad_out = 1'b0;`
67			`assign ps2_data_pad_out = 1'b0;`
68			`assign ramadv_n_pad_out = 1'b1;`
69			`assign ramclk_pad_out = 1'b0;`
70			`assign ramcre_pad_out = 1'b0;`
71			`assign ramcs_pad_out = 1'b0;`
72			`assign ramlb_n_pad_out = 1'b1;`
73			`assign ramub_n_pad_out = 1'b1;`
74			`assign rs_tx_pad_out = 1'b1;`
75			`assign rts_pad_out = 1'b0;`
76			`assign txd_pad_out = 1'b1;`
77			`assign usbrdy_pad_out = 1'b0;`
78			`assign vga_blue_pad_out = 2'b00;`
79			`assign vga_green_pad_out = 3'b000;`
80			`assign vga_hsync_n_pad_out = 1'b1;`
81			`assign vga_red_pad_out = 3'b000;`
82			`assign vga_vsync_n_pad_out = 1'b1;`
83
84
85

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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [rtl/] [verilog/] [top] - Blame information for rev 135