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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [rtl/] [xml/] [fpgas_iceskate_core.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
 
digilentinc.com
nexys2
iceskate
core
 

 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
  
    
      destination
      iceskate_core
    
  

 

 
 
 
 
 
 

 
 
 
 
 
 
 
  
 
 
              
              padring:*Simulation:*
              
              
                                   ipxact:library="nexys2"
                                   ipxact:name="iceskate"
                                   ipxact:version="CORE"/>
              
              
 
 
 
 
 
 
              
              verilog:*Simulation:*
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="verilog"/>
              
              
 
              
              common:*common:*
              Verilog
              
                     
                            fs-common
                     
              
 
              
              sim:*Simulation:*
              Verilog
              
                     
                            fs-sim
                     
              
 
 
              
              syn:*Synthesis:*
              Verilog
              
                     
                            fs-sim
                     
              
 
      
 
 

  CLOCK_FREQ50
  CLOCK_PLL_MULT2
  CLOCK_PLL_DIV4
  CLOCK_PLL_SIZE4
  CLOCK_SRC0
  RESET_SENSE0
  JTAG_USER1_WIDTH8
  JTAG_USER1_RESET8'h12
  JTAG_USER2_WIDTH8
  JTAG_USER2_RESET8'h78
  CHIP_ID32'h12345678
 

 
 
 
 
 
 
 
 
   tclk_pad_in
 wire
  in
   
 
 
 
 
    trst_n_pad_in
 wire
  in
   
  
 
 
   tms_pad_in
 wire
  in
   
  
 
 
   tdi_pad_in
 wire
  in
   
  
 
 
    tdo_pad_out
 wire
  out
   
  
 
 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
 
 
 
      
        
        ../verilog/top
        verilogSourcefragment
      
 
 
 
 
      
        ../verilog
        verilogSourcelibraryDir
      
 
 
 
   
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/iceskate_core
        verilogSourcemodule
      
 
 
 
 
 
 
   
 
 
 
 
 

 
 
 
 
 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [rtl/] [xml/] [fpgas_iceskate_core.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36
37			`digilentinc.com`
38			`nexys2`
39			`iceskate`
40			`core`
41
42
43
44
45			`gen_verilog`
46			`104.0`
47			`none`
48			`:common:`
49			`tools/verilog/gen_verilog`
50
51
52			`destination`
53			`iceskate_core`
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
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71
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76
77			`padring:Simulation:`
78
79
80			`ipxact:library="nexys2"`
81			`ipxact:name="iceskate"`
82			`ipxact:version="CORE"/>`
83
84
85
86
87
88
89
90
91
92			`verilog:Simulation:`
93
94
95			`ipxact:library="Testbench"`
96			`ipxact:name="toolflow"`
97			`ipxact:version="verilog"/>`
98
99
100
101
102			`common:common:`
103			`Verilog`
104
105
106			`fs-common`
107
108
109
110
111			`sim:Simulation:`
112			`Verilog`
113
114
115			`fs-sim`
116
117
118
119
120
121			`syn:Synthesis:`
122			`Verilog`
123
124
125			`fs-sim`
126
127
128
129
130
131
132
133			`CLOCK_FREQ50`
134			`CLOCK_PLL_MULT2`
135			`CLOCK_PLL_DIV4`
136			`CLOCK_PLL_SIZE4`
137			`CLOCK_SRC0`
138			`RESET_SENSE0`
139			`JTAG_USER1_WIDTH8`
140			`JTAG_USER1_RESET8'h12`
141			`JTAG_USER2_WIDTH8`
142			`JTAG_USER2_RESET8'h78`
143			`CHIP_ID32'h12345678`
144
145
146
147
148
149
150
151
152
153
154			`tclk_pad_in`
155			`wire`
156			`in`
157
158
159
160
161
162			`trst_n_pad_in`
163			`wire`
164			`in`
165
166
167
168
169			`tms_pad_in`
170			`wire`
171			`in`
172
173
174
175
176			`tdi_pad_in`
177			`wire`
178			`in`
179
180
181
182
183			`tdo_pad_out`
184			`wire`
185			`out`
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203			`fs-common`
204
205
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207
208
209
210			`../verilog/top`
211			`verilogSourcefragment`
212
213
214
215
216
217
218			`../verilog`
219			`verilogSourcelibraryDir`
220
221
222
223
224
225
226
227
228			`fs-sim`
229
230
231
232			`../verilog/copyright`
233			`verilogSourceinclude`
234
235
236
237
238			`../verilog/common/iceskate_core`
239			`verilogSourcemodule`
240
241
242
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