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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [rtl/] [xml/] [fpgas_iceskate_default.xml] - Blame information for rev 135

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xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014
http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">
digilentinc.com
nexys2
iceskate
default
 

 
 

  gen_verilog
  104.0
  none
  :*common:*
  tools/verilog/gen_verilog
    
    
      destination
      iceskate_default
    
  

 

 
 
 
 
 

 
 
  
   
     JTAG
    
   
  
 
  
 
 
 
    
      JTAG
      JTAG
    
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
    
     padring:*Simulation:*
     
     
                          ipxact:library="nexys2"
                          ipxact:name="iceskate"
                          ipxact:version="padring"/>
     
    
 
 
    
     verilog:*Simulation:*
     
     
                          ipxact:library="Testbench"
                          ipxact:name="toolflow"
                          ipxact:version="verilog"/>
     
    
 
 
 
    
    common:*common:*
    Verilog
    
    fs-common
    
 
 
 
 
 
    
    sim:*Simulation:*
    Verilog
    
    fs-sim
    
 
 
    
    syn:*Synthesis:*
    Verilog
    
    fs-sim
    
 
 
 
 
              
              doc:*Simulation:*
              
              
                                   ipxact:library="Testbench"
                                   ipxact:name="toolflow"
                                   ipxact:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
 
 
 
 
 
 
 
   tclk_pad_in
 wire
  in
   
 
 
 
 
    trst_n_pad_in
 wire
  in
   
  
 
 
   tms_pad_in
 wire
  in
   
  
 
 
   tdi_pad_in
 wire
  in
   
  
 
 
    tdo_pad_out
 wire
  out
   
  
 
 
 
 
 
 

 
 
 
 
  
 
 
 
    
      fs-sim
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/iceskate_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/sim/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
    
      fs-syn
 
      
        
        ../verilog/copyright
        verilogSourceinclude
      
 
      
        
        ../verilog/common/iceskate_default
        verilogSourcemodule
      
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
    
      fs-lint
 
      
        dest_dir
        ../views/syn/
        verilogSourcelibraryDir
      
 
    
 
 
 
 
 
 
 
 
 
  
 
 
 
 
 
 

 
 
 
 
 
 

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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [rtl/] [xml/] [fpgas_iceskate_default.xml] - Blame information for rev 135

Line No.	Rev	Author	Line
1	135	jt_eaton
2
30
31			`xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.accellera.org/XMLSchema/IPXACT/1685-2014`
35			`http://www.accellera.org/XMLSchema/IPXACT/1685-2014/index.xsd">`
36			`digilentinc.com`
37			`nexys2`
38			`iceskate`
39			`default`
40
41
42
43
44
45			`gen_verilog`
46			`104.0`
47			`none`
48			`:common:`
49			`tools/verilog/gen_verilog`
50
51
52			`destination`
53			`iceskate_default`
54
55
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67
68
69			`JTAG`
70
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79			`JTAG`
80			`JTAG`
81
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100
101			`padring:Simulation:`
102
103
104			`ipxact:library="nexys2"`
105			`ipxact:name="iceskate"`
106			`ipxact:version="padring"/>`
107
108
109
110
111
112			`verilog:Simulation:`
113
114
115			`ipxact:library="Testbench"`
116			`ipxact:name="toolflow"`
117			`ipxact:version="verilog"/>`
118
119
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123
124			`common:common:`
125			`Verilog`
126
127			`fs-common`
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135			`sim:Simulation:`
136			`Verilog`
137
138			`fs-sim`
139
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141
142
143			`syn:Synthesis:`
144			`Verilog`
145
146			`fs-sim`
147
148
149
150
151
152
153			`doc:Simulation:`
154
155
156			`ipxact:library="Testbench"`
157			`ipxact:name="toolflow"`
158			`ipxact:version="documentation"/>`
159
160			`:Documentation:`
161			`Verilog`
162
163
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173
174			`tclk_pad_in`
175			`wire`
176			`in`
177
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181
182			`trst_n_pad_in`
183			`wire`
184			`in`
185
186
187
188
189			`tms_pad_in`
190			`wire`
191			`in`
192
193
194
195
196			`tdi_pad_in`
197			`wire`
198			`in`
199
200
201
202
203			`tdo_pad_out`
204			`wire`
205			`out`
206
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224			`fs-sim`
225
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227
228			`../verilog/copyright`
229			`verilogSourceinclude`
230
231
232
233
234			`../verilog/common/iceskate_default`
235			`verilogSourcemodule`
236
237
238
239			`dest_dir`
240			`../views/sim/`
241			`verilogSourcelibraryDir`
242
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249
250			`fs-syn`
251
252
253
254			`../verilog/copyright`
255			`verilogSourceinclude`
256
257
258
259
260			`../verilog/common/iceskate_default`
261			`verilogSourcemodule`
262
263
264
265			`dest_dir`
266			`../views/syn/`
267			`verilogSourcelibraryDir`
268
269
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273
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275
276
277			`fs-lint`
278
279
280			`dest_dir`
281			`../views/syn/`
282			`verilogSourcelibraryDir`
283
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