URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [sim/] [icarus/] [default/] [test_define] - Blame information for rev 135

Details | Compare with Previous | View Log


reg actual;
 
 
parameter       EXTEST=4'b0000;
parameter       SAMPLE=4'b0001;
parameter       HIGHZ_MODE=4'b0010;
parameter       CHIP_ID_ACCESS=4'b0011;
parameter       CLAMP=4'b1000;
parameter       RPC_DATA=4'b1010;
parameter       RPC_ADD=4'b1001;
parameter       BYPASS=4'b1111;
parameter       INST_RETURN=4'b1101;
 
initial
begin
 
test.btn_reg <= 4'b0000;
test.sw_reg <= 8'b00000000;
 
$display("              ");
$display("              ===================================================");
$display("              Test Start");
$display("              ===================================================");
$display("              ");
test.cg.next(2);
test.jtag_model.enable_tclk;
test.cg.next(20);
 
test.cg.next(20);
test.jtag_model.enable_trst_n;
test.jtag_model.enable_reset;
test.jtag_model.init;
test.cg.next(10);
test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);
test.cg.next(100);
test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);
 
 
 
test.cg.exit;
end
 
 
 
 
 
 
task automatic  Shift_Cmp_8;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  8;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
task automatic  Shift_Cmp_24;    // Initialize boundary register with outputs disabled
                         // This tasks starts at RT_IDLE and ends at SHIFT_DR
 
  parameter [15:0] LENGTH =  24;
 
 
  input [LENGTH:1]  Dataout;
  input [LENGTH:1]  DataExp;
 
  integer i;
 
  reg [LENGTH:1]  DataBack;
 
  begin
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR
    for (i = 1; i <= LENGTH; i = i+1)
       test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);
    $display  ("%t  %m    Shift_data_register    wr-%h  exp-%h rd-%h    ",$realtime,Dataout,DataExp,DataBack  );
 
   if (DataBack  !== DataExp )
   begin
   test.cg.fail  (" Shift_cmp  receive error  ");
   end
 
    test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR
    test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE
  end
endtask // ShiftRegister
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton	`reg actual;`
2
3
4			`parameter EXTEST=4'b0000;`
5			`parameter SAMPLE=4'b0001;`
6			`parameter HIGHZ_MODE=4'b0010;`
7			`parameter CHIP_ID_ACCESS=4'b0011;`
8			`parameter CLAMP=4'b1000;`
9			`parameter RPC_DATA=4'b1010;`
10			`parameter RPC_ADD=4'b1001;`
11			`parameter BYPASS=4'b1111;`
12			`parameter INST_RETURN=4'b1101;`
13
14			`initial`
15			`begin`
16
17			`test.btn_reg <= 4'b0000;`
18			`test.sw_reg <= 8'b00000000;`
19
20			`$display(" ");`
21			`$display(" ===================================================");`
22			`$display(" Test Start");`
23			`$display(" ===================================================");`
24			`$display(" ");`
25			`test.cg.next(2);`
26			`test.jtag_model.enable_tclk;`
27			`test.cg.next(20);`
28
29			`test.cg.next(20);`
30			`test.jtag_model.enable_trst_n;`
31			`test.jtag_model.enable_reset;`
32			`test.jtag_model.init;`
33			`test.cg.next(10);`
34			`test.jtag_model.LoadTapInst(EXTEST,INST_RETURN);`
35			`test.cg.next(100);`
36			`test.jtag_model.LoadTapInst(CLAMP,INST_RETURN);`
37
38
39
40			`test.cg.exit;`
41			`end`
42
43
44
45
46
47
48			`task automatic Shift_Cmp_8; // Initialize boundary register with outputs disabled`
49			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
50
51			`parameter [15:0] LENGTH = 8;`
52
53
54			`input [LENGTH:1] Dataout;`
55			`input [LENGTH:1] DataExp;`
56
57			`integer i;`
58
59			`reg [LENGTH:1] DataBack;`
60
61			`begin`
62			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
63			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
64			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
65			`for (i = 1; i <= LENGTH; i = i+1)`
66			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
67			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
68
69			`if (DataBack !== DataExp )`
70			`begin`
71			`test.cg.fail (" Shift_cmp receive error ");`
72			`end`
73
74			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
75			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
76			`end`
77			`endtask // ShiftRegister`
78
79
80
81
82			`task automatic Shift_Cmp_24; // Initialize boundary register with outputs disabled`
83			`// This tasks starts at RT_IDLE and ends at SHIFT_DR`
84
85			`parameter [15:0] LENGTH = 24;`
86
87
88			`input [LENGTH:1] Dataout;`
89			`input [LENGTH:1] DataExp;`
90
91			`integer i;`
92
93			`reg [LENGTH:1] DataBack;`
94
95			`begin`
96			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);// Transition from RT_IDLE to SELECT_DR`
97			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from SELECT_DR to CAPTURE_DR`
98			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from CAPTURE_DR to SHIFT_DR`
99			`for (i = 1; i <= LENGTH; i = i+1)`
100			`test.jtag_model.Clk_bit((i==LENGTH),Dataout[i],DataBack[i]);`
101			`$display ("%t %m Shift_data_register wr-%h exp-%h rd-%h ",$realtime,Dataout,DataExp,DataBack );`
102
103			`if (DataBack !== DataExp )`
104			`begin`
105			`test.cg.fail (" Shift_cmp receive error ");`
106			`end`
107
108			`test.jtag_model.Clk_bit(1'b1,1'b0,actual);//Transition from EXIT1-DR to UPDATE-DR`
109			`test.jtag_model.Clk_bit(1'b0,1'b0,actual);// Transition from UPDATE-DR to IDLE`
110			`end`
111			`endtask // ShiftRegister`
112
113
114
115
116
117
118

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [sim/] [icarus/] [default/] [test_define] - Blame information for rev 135