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[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 135

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reg [3:0]   btn_reg;
 
 
 
reg [7:0]   sw_reg;
 
 
 
 
assign A_CLK   = clk;
assign CTS     = reset;
assign SW      = sw_reg;
assign BTN     = btn_reg;
 
 
 
 
assign STOP = 1'b0;
assign BAD = 1'b0;
 
 

Line No.	Rev	Author	Line
1	135	jt_eaton
2
3
4			`reg [3:0] btn_reg;`
5
6
7
8			`reg [7:0] sw_reg;`
9
10
11
12
13			`assign A_CLK = clk;`
14			`assign CTS = reset;`
15			`assign SW = sw_reg;`
16			`assign BTN = btn_reg;`
17
18
19
20
21			`assign STOP = 1'b0;`
22			`assign BAD = 1'b0;`
23
24

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [digilentinc.com/] [nexys2/] [ip/] [iceskate/] [sim/] [testbenches/] [verilog/] [tb.ext] - Blame information for rev 135