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[/] [socgen/] [trunk/] [Projects/] [lattice.com/] [fpgas/] [ip/] [iceskate/] [rtl/] [verilog/] [top] - Blame information for rev 135

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wire clk;
wire reset;
 
assign clk            = clk_pad_in;
 
 
reg [31:0] COUNTER;
 
always@(posedge clk)
begin
               COUNTER <= COUNTER + 32'h00000001;
end
 
 
 
 
 
 
 
 
 
assign   led1_pad_out    = COUNTER[29];
assign   led2_pad_out    = COUNTER[27];
assign   led3_pad_out    = COUNTER[25];
assign   led4_pad_out    = COUNTER[23];
assign   led5_pad_out    = COUNTER[22];
 
 
 
 
assign   j1_10_pad_out = ctsn_pad_in ^ dcdn_pad_in ^ dsrn_pad_in ^ rs232_rx_pad_in ^ rxd_pad_in ;
assign   dtrn_pad_out    = 1'b1;
assign   j1_3_pad_out             = 1'b0;
assign   j1_4_pad_out                      = 1'b0;
assign   j1_5_pad_out                               = 1'b0;
assign   j1_6_pad_out                               = 1'b0;
assign   j1_7_pad_out                               = 1'b0;
assign   j1_8_pad_out                               = 1'b0;
assign   j1_9_pad_out                               = 1'b0;
assign   j3_10_pad_out                               = 1'b0;
assign   j3_3_pad_out                               = 1'b0;
assign   j3_4_pad_out                               = 1'b0;
assign   j3_5_pad_out                               = 1'b0;
assign   j3_6_pad_out                               = 1'b0;
assign   j3_7_pad_out                               = 1'b0;
assign   j3_8_pad_out                               = 1'b0;
assign   j3_9_pad_out                               = 1'b0;
assign   pmod_1_pad_out                               = 1'b0;
assign   pmod_10_pad_out                               = 1'b0;
assign   pmod_2_pad_out                               = 1'b0;
assign   pmod_3_pad_out                               = 1'b0;
assign   pmod_4_pad_out                               = 1'b0;
assign   pmod_7_pad_out                               = 1'b0;
assign   pmod_8_pad_out                               = 1'b0;
assign   pmod_9_pad_out                               = 1'b0;
assign   rs232_tx_pad_out                               = 1'b1;
assign   rtsn_pad_out           = 1'b1;
assign   sd_pad_out           = 1'b1;
assign   txd_pad_out                 = 1'b1;

Line No.	Rev	Author	Line
1	135	jt_eaton
2			`wire clk;`
3			`wire reset;`
4
5			`assign clk = clk_pad_in;`
6
7
8			`reg [31:0] COUNTER;`
9
10			`always@(posedge clk)`
11			`begin`
12			`COUNTER <= COUNTER + 32'h00000001;`
13			`end`
14
15
16
17
18
19
20
21
22
23			`assign led1_pad_out = COUNTER[29];`
24			`assign led2_pad_out = COUNTER[27];`
25			`assign led3_pad_out = COUNTER[25];`
26			`assign led4_pad_out = COUNTER[23];`
27			`assign led5_pad_out = COUNTER[22];`
28
29
30
31
32			`assign j1_10_pad_out = ctsn_pad_in ^ dcdn_pad_in ^ dsrn_pad_in ^ rs232_rx_pad_in ^ rxd_pad_in ;`
33			`assign dtrn_pad_out = 1'b1;`
34			`assign j1_3_pad_out = 1'b0;`
35			`assign j1_4_pad_out = 1'b0;`
36			`assign j1_5_pad_out = 1'b0;`
37			`assign j1_6_pad_out = 1'b0;`
38			`assign j1_7_pad_out = 1'b0;`
39			`assign j1_8_pad_out = 1'b0;`
40			`assign j1_9_pad_out = 1'b0;`
41			`assign j3_10_pad_out = 1'b0;`
42			`assign j3_3_pad_out = 1'b0;`
43			`assign j3_4_pad_out = 1'b0;`
44			`assign j3_5_pad_out = 1'b0;`
45			`assign j3_6_pad_out = 1'b0;`
46			`assign j3_7_pad_out = 1'b0;`
47			`assign j3_8_pad_out = 1'b0;`
48			`assign j3_9_pad_out = 1'b0;`
49			`assign pmod_1_pad_out = 1'b0;`
50			`assign pmod_10_pad_out = 1'b0;`
51			`assign pmod_2_pad_out = 1'b0;`
52			`assign pmod_3_pad_out = 1'b0;`
53			`assign pmod_4_pad_out = 1'b0;`
54			`assign pmod_7_pad_out = 1'b0;`
55			`assign pmod_8_pad_out = 1'b0;`
56			`assign pmod_9_pad_out = 1'b0;`
57			`assign rs232_tx_pad_out = 1'b1;`
58			`assign rtsn_pad_out = 1'b1;`
59			`assign sd_pad_out = 1'b1;`
60			`assign txd_pad_out = 1'b1;`

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[/] [socgen/] [trunk/] [Projects/] [lattice.com/] [fpgas/] [ip/] [iceskate/] [rtl/] [verilog/] [top] - Blame information for rev 135