This component comes from the opencores t6507lp project and makes it socgen compatible. The original project checked in by Gabriel Oshiro Zardo and Samuel Nascimento Pagliarini was a atari 2600 on a chip. This project only takes the t6507 processor and uses it as a 6502. It had some documentation and a test suite that was somewhat working.
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I chose it because a 6502 is a useful module and had clean partitioning. The following changes were made:
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1) Converted to a full 16 bit address bus.
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also hardcoded the 8 bit data bus. Hasn't changed in thirty five years.
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2) Converted parameters to `defines
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3) Converted reset to synchronous active high
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4) Converted test suite to socgen format
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Each test is in it's own subdirectory and any needed code is assembled and loaded into sram
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5) Design had no reset/interrupt vectors. Added reset vector. May add interupt(s) later.
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6) Added enable logic so that it could work with synchronous sram
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7) Design doesn't appear to be fully functional.
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CLC followed by BCC missed the offset by one clock cycle.
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JSR doesn't push high address on stack. puts wrong data in page 00
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Branch backwards doesn't work.
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read/modify/write did not work
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pha pushed onto page 0
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pha data latched one clock to late
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jmp indirect didn't work
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8) Split T6502_fsm into smaller blocks for ease of documenting and verifying
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9) Move branch decision logic into sequencer block
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10) removed BCD logic
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11) moved alu_opcode to instr_decode block
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12) created datapath logic for alu_operand_a, alu_operand_b and alu_operand_c
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13) split alu into alu_control and alu blocks
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14) reworked the inst_decode signals to alu and pulled datapath out of sequencer
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15) removed the latched alu_result. Outside of alu now uses raw
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This appears to be a work in progress with numerous issues. I fixed enough of them so that I can
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synthesize into an fpga and it runs the io_poll program on a Nexys2 Board. I will commit this as
