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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [doc/] [sym/] [T6502_ctrl.sym] - Blame information for rev 135

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Line No. Rev Author Line
1 135 jt_eaton 
v 20100214 1
2 
B 300 0  4400 3100 3 60 0 0 -1 -1 0 -1 -1 -1 -1 -1
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T 400 3250   5 10 1 1 0 0 1 1
4 
device=T6502_ctrl
5 
T 400 3450 5 10 1 1 0 0 1 1
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refdes=U?
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T 400 3600    0 10 0 1 0 0 1 1
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vendor=opencores.org
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T 400 3600    0 10 0 1 0 0 1 1
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library=Mos6502
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T 400 3600    0 10 0 1 0 0 1 1
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component=T6502
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T 400 3600    0 10 0 1 0 0 1 1
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version=ctrl
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P 300 200 0 200 10 1 1
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{
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T 400 200 5 10 1 1 0 1 1 1
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pinnumber=timer_irq[1:0]
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T 400 200 5 10 0 1 0 1 1 1
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pinseq=1
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}
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P 300 400 0 400 10 1 1
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{
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T 400 400 5 10 1 1 0 1 1 1
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pinnumber=pg0_add[7:0]
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T 400 400 5 10 0 1 0 1 1 1
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pinseq=2
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}
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P 300 600 0 600 10 1 1
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{
31 
T 400 600 5 10 1 1 0 1 1 1
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pinnumber=mem_wdata[15:0]
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T 400 600 5 10 0 1 0 1 1 1
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pinseq=3
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}
36 
P 300 800 0 800 10 1 1
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{
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T 400 800 5 10 1 1 0 1 1 1
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pinnumber=mem_addr[0:0]
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T 400 800 5 10 0 1 0 1 1 1
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pinseq=4
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}
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P 300 1000 0 1000 10 1 1
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{
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T 400 1000 5 10 1 1 0 1 1 1
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pinnumber=ext_irq_in[2:0]
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T 400 1000 5 10 0 1 0 1 1 1
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pinseq=5
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}
50 
P 300 1200 0 1200 4 0 1
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{
52 
T 400 1200 5 10 1 1 0 1 1 1
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pinnumber=tx_irq
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T 400 1200 5 10 0 1 0 1 1 1
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pinseq=6
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}
57 
P 300 1400 0 1400 4 0 1
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{
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T 400 1400 5 10 1 1 0 1 1 1
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pinnumber=rx_irq
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T 400 1400 5 10 0 1 0 1 1 1
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pinseq=7
63 
}
64 
P 300 1600 0 1600 4 0 1
65 
{
66 
T 400 1600 5 10 1 1 0 1 1 1
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pinnumber=ps2_data_avail
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T 400 1600 5 10 0 1 0 1 1 1
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pinseq=8
70 
}
71 
P 300 1800 0 1800 4 0 1
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{
73 
T 400 1800 5 10 1 1 0 1 1 1
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pinnumber=pg0_wr
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T 400 1800 5 10 0 1 0 1 1 1
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pinseq=9
77 
}
78 
P 300 2000 0 2000 4 0 1
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{
80 
T 400 2000 5 10 1 1 0 1 1 1
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pinnumber=pg0_rd
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T 400 2000 5 10 0 1 0 1 1 1
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pinseq=10
84 
}
85 
P 300 2200 0 2200 4 0 1
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{
87 
T 400 2200 5 10 1 1 0 1 1 1
88 
pinnumber=mem_wr
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T 400 2200 5 10 0 1 0 1 1 1
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pinseq=11
91 
}
92 
P 300 2400 0 2400 4 0 1
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{
94 
T 400 2400 5 10 1 1 0 1 1 1
95 
pinnumber=mem_rd
96 
T 400 2400 5 10 0 1 0 1 1 1
97 
pinseq=12
98 
}
99 
P 300 2600 0 2600 4 0 1
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{
101 
T 400 2600 5 10 1 1 0 1 1 1
102 
pinnumber=mem_cs
103 
T 400 2600 5 10 0 1 0 1 1 1
104 
pinseq=13
105 
}
106 
P 300 2800 0 2800 4 0 1
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{
108 
T 400 2800 5 10 1 1 0 1 1 1
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pinnumber=clk
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T 400 2800 5 10 0 1 0 1 1 1
111 
pinseq=14
112 
}
113 
P 4700 200 5000 200 10 1 1
114 
{
115 
T 4600 200 5  10 1 1 0 7 1 1
116 
pinnumber=mem_rdata[15:0]
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T 4600 200 5  10 0 1 0 7 1 1
118 
pinseq=15
119 
}
120 
P 4700 400 5000 400 10 1 1
121 
{
122 
T 4600 400 5  10 1 1 0 7 1 1
123 
pinnumber=io_module_vic_irq_in[7:0]
124 
T 4600 400 5  10 0 1 0 7 1 1
125 
pinseq=16
126 
}
127 
P 4700 600 5000 600 10 1 1
128 
{
129 
T 4600 600 5  10 1 1 0 7 1 1
130 
pinnumber=io_module_pic_irq_in[7:0]
131 
T 4600 600 5  10 0 1 0 7 1 1
132 
pinseq=17
133 
}
134 
P 4700 800 5000 800 10 1 1
135 
{
136 
T 4600 800 5  10 1 1 0 7 1 1
137 
pinnumber=cpu_pg0_data[7:0]
138 
T 4600 800 5  10 0 1 0 7 1 1
139 
pinseq=18
140 
}

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