URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Blame information for rev 133

Go to most recent revision | Details | Compare with Previous | View Log





xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
ctrl  default
 

 
 
 

  elab_verilog
  102.1
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog
    
    
      configuration
      ctrl_default
    
    
      dest_dir
      io_ports
    
  
 

 
 
 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      top.ctrl
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
   
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.ctrl
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top.ctrl
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 

 
 
 
 
 
 
 

 
 
 
 
 
   
 
 
              
              Hierarchical
 
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="ctrl.design"/>
              
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
     
     commoncommon
     Verilog
     
     fs-common
     
 
     
     sim:*Simulation:*
     Verilog
     
     fs-sim
     
 
 
     
     syn:*Synthesis:*
     Verilog
     
     fs-syn
     
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
   
 
 
 

 

    VEC_TABLE8'hff

 
 
    PG0_WIDTH8
    PG0_ADDR7
 
    PG0_WORDS128
 
    PG0_WRITETHRU0
 
 
    PG0_DEFAULT8'hff
 
 
 
 

 
 
 

 
 

clk
wire
in

 
 

cpu_pg0_data
wire
out70

 
 
 

pg00_ram_rd
wire
out

 
 

pg00_ram_l_wr
wire
out

 
 

pg00_ram_h_wr
wire
out

 
 
 
 
 
 
 
 

io_module_pic_irq_in
wire
out70

 
 
 
 
 

io_module_vic_irq_in
wire
out70

 
 
 
 
 
 
 
 

mem_rdata
wire
out150

 
 
 

mem_wdata
wire
in150

 
 
 
 
 

pg0_add
wire
in70

 
 

mem_addr
wire
in00

 
 

mem_cs
wire
in

 
 
 
 
mem_wr
wire
in

 
 
pg0_wr
wire
in

 
 
mem_rd
wire
in

 
 
 
pg0_rd
wire
in

 
 
 
 
 

timer_irq
wire
in10

 
 
 
rx_irq
wire
in

 
 
tx_irq
wire
in

 
 
ps2_data_avail
wire
in

 
 
 
ext_irq_in
wire
in20

 
 

 

 
 
 
 
 
 

 
 
 
 
 
 

Browse

Tools

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Blame information for rev 133

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`ctrl default`
41
42
43
44
45
46	133	jt_eaton
47			`elab_verilog`
48			`102.1`
49			`none`
50			`:Simulation:`
51			`./tools/verilog/elab_verilog`
52
53
54			`configuration`
55			`ctrl_default`
56
57
58			`dest_dir`
59			`io_ports`
60
61
62	131	jt_eaton
63	133	jt_eaton
64	131	jt_eaton
65
66
67
68	133	jt_eaton
69
70
71	131	jt_eaton
72			`gen_verilog`
73			`104.0`
74			`none`
75			`common`
76			`./tools/verilog/gen_verilog`
77
78
79			`destination`
80			`top.ctrl`
81
82
83			`dest_dir`
84			`../verilog`
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102			`fs-common`
103
104
105
106			`../verilog/top.rtl`
107			`verilogSourcefragment`
108
109
110
111
112
113
114
115
116			`fs-sim`
117
118
119
120			`../verilog/copyright.v`
121			`verilogSourceinclude`
122
123
124
125
126			`../verilog/common/top.ctrl`
127			`verilogSourcemodule`
128
129
130
131
132
133
134
135			`fs-syn`
136
137
138
139			`../verilog/copyright.v`
140			`verilogSourceinclude`
141
142
143
144
145			`../verilog/common/top.ctrl`
146			`verilogSourcemodule`
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173	133	jt_eaton
174	131	jt_eaton
175	133	jt_eaton	`Hierarchical`
176
177
178			`spirit:library="Mos6502"`
179			`spirit:name="T6502"`
180			`spirit:version="ctrl.design"/>`
181
182
183
184
185
186	131	jt_eaton	`verilog`
187
188
189			`spirit:library="Testbench"`
190			`spirit:name="toolflow"`
191			`spirit:version="verilog"/>`
192
193
194
195
196
197
198
199
200			`commoncommon`
201			`Verilog`
202
203			`fs-common`
204
205
206
207			`sim:Simulation:`
208			`Verilog`
209
210			`fs-sim`
211
212
213
214
215			`syn:Synthesis:`
216			`Verilog`
217
218			`fs-syn`
219
220
221
222
223
224			`doc`
225
226
227			`spirit:library="Testbench"`
228			`spirit:name="toolflow"`
229			`spirit:version="documentation"/>`
230
231			`:Documentation:`
232			`Verilog`
233
234
235
236
237
238
239
240	133	jt_eaton
241	131	jt_eaton
242	133	jt_eaton
243			`VEC_TABLE8'hff`
244
245	131	jt_eaton
246
247	133	jt_eaton	`PG0_WIDTH8`
248			`PG0_ADDR7`
249
250			`PG0_WORDS128`
251
252			`PG0_WRITETHRU0`
253
254
255			`PG0_DEFAULT8'hff`
256
257
258
259
260
261
262
263
264	131	jt_eaton
265
266
267
268			`clk`
269			`wire`
270			`in`
271
272
273
274
275			`cpu_pg0_data`
276			`wire`
277			`out70`
278
279
280
281
282
283			`pg00_ram_rd`
284			`wire`
285			`out`
286
287
288
289
290			`pg00_ram_l_wr`
291			`wire`
292			`out`
293
294
295
296
297			`pg00_ram_h_wr`
298			`wire`
299			`out`
300
301
302
303
304
305
306
307
308
309
310			`io_module_pic_irq_in`
311			`wire`
312			`out70`
313
314
315
316
317
318
319
320			`io_module_vic_irq_in`
321			`wire`
322			`out70`
323
324
325
326
327
328
329
330
331
332
333			`mem_rdata`
334			`wire`
335			`out150`
336
337
338
339
340
341			`mem_wdata`
342			`wire`
343			`in150`
344
345
346
347
348
349
350
351			`pg0_add`
352			`wire`
353			`in70`
354
355
356
357
358			`mem_addr`
359			`wire`
360			`in00`
361
362
363
364
365			`mem_cs`
366			`wire`
367			`in`
368
369
370
371
372
373			`mem_wr`
374			`wire`
375			`in`
376
377
378
379			`pg0_wr`
380			`wire`
381			`in`
382
383
384
385			`mem_rd`
386			`wire`
387			`in`
388
389
390
391
392			`pg0_rd`
393			`wire`
394			`in`
395
396
397
398
399
400
401
402			`timer_irq`
403			`wire`
404			`in10`
405
406
407
408
409			`rx_irq`
410			`wire`
411			`in`
412
413
414
415			`tx_irq`
416			`wire`
417			`in`
418
419
420
421			`ps2_data_avail`
422			`wire`
423			`in`
424
425
426
427
428			`ext_irq_in`
429			`wire`
430			`in20`
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449