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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
ctrl  default
 

 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      T6502_ctrl
    
  

 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
   
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/T6502_ctrl
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-syn
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/T6502_ctrl
        verilogSourcemodule
      
 
 
 
 
   
 
 
 
 

 
 
 
 
 
 
 

 
 
 
 
 
   
 
 
              
              Hierarchical
 
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="ctrl.design"/>
              
 
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
     
     commoncommon
     Verilog
     
     fs-common
     
 
     
     sim:*Simulation:*
     Verilog
     
     fs-sim
     
 
 
     
     syn:*Synthesis:*
     Verilog
     
     fs-syn
     
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
   
 
 
 

 

    VEC_TABLE8'hff

    PG0_WIDTH8
    PG0_ADDR7
    PG0_WORDS128
    PG0_WRITETHRU0

 
 
 

 
 

clk
wire
in

 
 

cpu_pg0_data
wire
out70

 
 
 

pg00_ram_rd
wire
out

 
 

pg00_ram_l_wr
wire
out

 
 

pg00_ram_h_wr
wire
out

 
 
 
 
 
 
 
 

io_module_pic_irq_in
wire
out70

 
 
 
 
 

io_module_vic_irq_in
wire
out70

 
 
 
 
 
 
 
 

mem_rdata
wire
out150

 
 
 

mem_wdata
wire
in150

 
 
 
 
 

pg0_add
wire
in70

 
 

mem_addr
wire
in00

 
 

mem_cs
wire
in

 
 
 
 
mem_wr
wire
in

 
 
pg0_wr
wire
in

 
 
mem_rd
wire
in

 
 
 
pg0_rd
wire
in

 
 
 
 
 

timer_irq
wire
in10

 
 
 
rx_irq
wire
in

 
 
tx_irq
wire
in

 
 
ps2_data_avail
wire
in

 
 
 
ext_irq_in
wire
in20

 
 

 

 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_ctrl.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`ctrl default`
41
42
43
44	133	jt_eaton
45	131	jt_eaton	`gen_verilog`
46			`104.0`
47			`none`
48			`common`
49			`./tools/verilog/gen_verilog`
50
51
52			`destination`
53	134	jt_eaton	`T6502_ctrl`
54	131	jt_eaton
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71			`fs-common`
72
73
74
75			`../verilog/top.rtl`
76			`verilogSourcefragment`
77
78
79
80
81
82
83
84
85			`fs-sim`
86
87
88
89			`../verilog/copyright.v`
90			`verilogSourceinclude`
91
92
93
94
95	134	jt_eaton	`../verilog/common/T6502_ctrl`
96	131	jt_eaton	`verilogSourcemodule`
97
98
99
100
101
102
103
104			`fs-syn`
105
106
107
108			`../verilog/copyright.v`
109			`verilogSourceinclude`
110
111
112
113
114	134	jt_eaton	`../verilog/common/T6502_ctrl`
115	131	jt_eaton	`verilogSourcemodule`
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
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140
141
142	133	jt_eaton
143	131	jt_eaton
144	133	jt_eaton	`Hierarchical`
145
146
147			`spirit:library="Mos6502"`
148			`spirit:name="T6502"`
149			`spirit:version="ctrl.design"/>`
150
151
152
153
154
155	131	jt_eaton	`verilog`
156
157
158			`spirit:library="Testbench"`
159			`spirit:name="toolflow"`
160			`spirit:version="verilog"/>`
161
162
163
164
165
166
167
168
169			`commoncommon`
170			`Verilog`
171
172			`fs-common`
173
174
175
176			`sim:Simulation:`
177			`Verilog`
178
179			`fs-sim`
180
181
182
183
184			`syn:Synthesis:`
185			`Verilog`
186
187			`fs-syn`
188
189
190
191
192
193			`doc`
194
195
196			`spirit:library="Testbench"`
197			`spirit:name="toolflow"`
198			`spirit:version="documentation"/>`
199
200			`:Documentation:`
201			`Verilog`
202
203
204
205
206
207
208
209	133	jt_eaton
210	131	jt_eaton
211	133	jt_eaton
212			`VEC_TABLE8'hff`
213
214			`PG0_WIDTH8`
215			`PG0_ADDR7`
216			`PG0_WORDS128`
217			`PG0_WRITETHRU0`
218
219
220
221
222	131	jt_eaton
223
224
225
226			`clk`
227			`wire`
228			`in`
229
230
231
232
233			`cpu_pg0_data`
234			`wire`
235			`out70`
236
237
238
239
240
241			`pg00_ram_rd`
242			`wire`
243			`out`
244
245
246
247
248			`pg00_ram_l_wr`
249			`wire`
250			`out`
251
252
253
254
255			`pg00_ram_h_wr`
256			`wire`
257			`out`
258
259
260
261
262
263
264
265
266
267
268			`io_module_pic_irq_in`
269			`wire`
270			`out70`
271
272
273
274
275
276
277
278			`io_module_vic_irq_in`
279			`wire`
280			`out70`
281
282
283
284
285
286
287
288
289
290
291			`mem_rdata`
292			`wire`
293			`out150`
294
295
296
297
298
299			`mem_wdata`
300			`wire`
301			`in150`
302
303
304
305
306
307
308
309			`pg0_add`
310			`wire`
311			`in70`
312
313
314
315
316			`mem_addr`
317			`wire`
318			`in00`
319
320
321
322
323			`mem_cs`
324			`wire`
325			`in`
326
327
328
329
330
331			`mem_wr`
332			`wire`
333			`in`
334
335
336
337			`pg0_wr`
338			`wire`
339			`in`
340
341
342
343			`mem_rd`
344			`wire`
345			`in`
346
347
348
349
350			`pg0_rd`
351			`wire`
352			`in`
353
354
355
356
357
358
359
360			`timer_irq`
361			`wire`
362			`in10`
363
364
365
366
367			`rx_irq`
368			`wire`
369			`in`
370
371
372
373			`tx_irq`
374			`wire`
375			`in`
376
377
378
379			`ps2_data_avail`
380			`wire`
381			`in`
382
383
384
385
386			`ext_irq_in`
387			`wire`
388			`in20`
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407