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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 131

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 
 
 jtag
  
  
    
 
      
        shiftcapture_dr_clk
        jtag_shiftcapture_dr_clk
      
 
 
      
        test_logic_reset
        jtag_test_logic_reset
      
 
      
        capture_dr
        jtag_capture_dr
      
 
      
        shift_dr
        jtag_shift_dr
      
 
      
        update_dr_clk
        jtag_update_dr_clk
      
 
 
      
        tdi
        jtag_tdi
      
 
      
        tdo
        jtag_tdo
      
 
      
        select
        jtag_select
      
 
    
 
 
 
 

 
 

 
 
 
 

  elab_verilog
  103.0
  none
  :*Simulation:*
  ./tools/verilog/elab_verilog

 
 
 

  trace_bus
  103.0
  none
  :*Simulation:*
  ./tools/verilog/trace_bus
    
    
      path
      root.cpu
    
    
      bus_name
      cpu
    
  

 
 
 
 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      configuration
      default
    
    
      destination
      top
    
    
      dest_dir
      ../verilog
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
   
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/top
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-syn
 
      
        
        ../verilog/syn.v
        verilogSourceinclude
      
 
 
 
   
 
 

 
 
 
 
 
 
 

 
 

    CPU_ADD16
    RAM_WORDS2048
    RAM_ADD11
    ROM_WORDS4096
    ROM_ADD12
    PROG_ROM_WORDS4096
    PROG_ROM_ADD12
    VEC_TABLE8'hff
    UART_PRESCALE5'b01100
    UART_PRE_SIZE5
    UART_DIV0
    JTAG_SEL1

 
 
 
   
 
 
              
              Hierarchical
 
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
     
     commoncommon
     Verilog
     
     
 
     
     sim:*Simulation:*
      Verilog
     
     fs-sim
     
 
     
     syn:*Synthesis:*
      Verilog
     
     fs-sim
     
 
 
     
     syn2:*Synthesis:*
      Verilog
     
     fs-syn
     
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
   
 
 
 

 
 

ext_addr
wire
out231

 

ext_wdata
wire
out150

 

ext_rdata
wire
in150

 
 

ext_ub
wire
out

 
ext_wait
wire
in

 
ext_lb
wire
out

 
ext_rd
wire
out

 
ext_stb
wire
out

 
ext_wr
wire
out

 
ext_cs
wire
out10

 
 
alu_status
wire
out70

 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
 
gpio_0_out
wire
out70

 
gpio_0_oe
wire
out70

 
 
gpio_0_in
wire
in70

 
gpio_1_out
wire
out70

 
gpio_1_oe
wire
out70

 
 
gpio_1_in
wire
in70

 
ext_irq_in
wire
in30

 
 
 
 
jsp_data_out
wire
out70

 
 
 
wb_jsp_dat_i
wire
in70

 
 
biu_wr_strobe
wire
out

 
 
wb_jsp_stb_i
wire
in

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 131

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75			`jtag`
76
77
78
79
80
81			`shiftcapture_dr_clk`
82			`jtag_shiftcapture_dr_clk`
83
84
85
86
87			`test_logic_reset`
88			`jtag_test_logic_reset`
89
90
91
92			`capture_dr`
93			`jtag_capture_dr`
94
95
96
97			`shift_dr`
98			`jtag_shift_dr`
99
100
101
102			`update_dr_clk`
103			`jtag_update_dr_clk`
104
105
106
107
108			`tdi`
109			`jtag_tdi`
110
111
112
113			`tdo`
114			`jtag_tdo`
115
116
117
118			`select`
119			`jtag_select`
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136			`elab_verilog`
137			`103.0`
138			`none`
139			`:Simulation:`
140			`./tools/verilog/elab_verilog`
141
142
143
144
145
146			`trace_bus`
147			`103.0`
148			`none`
149			`:Simulation:`
150			`./tools/verilog/trace_bus`
151
152
153			`path`
154			`root.cpu`
155
156
157			`bus_name`
158			`cpu`
159
160
161
162
163
164
165
166
167
168			`gen_verilog`
169			`104.0`
170			`none`
171			`common`
172			`./tools/verilog/gen_verilog`
173
174
175			`configuration`
176			`default`
177
178
179			`destination`
180			`top`
181
182
183			`dest_dir`
184			`../verilog`
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205			`fs-common`
206
207
208
209			`../verilog/top.rtl`
210			`verilogSourcefragment`
211
212
213
214
215
216
217
218
219			`fs-sim`
220
221
222
223			`../verilog/copyright.v`
224			`verilogSourceinclude`
225
226
227
228
229			`../verilog/common/top`
230			`verilogSourcemodule`
231
232
233
234
235
236
237
238			`fs-syn`
239
240
241
242			`../verilog/syn.v`
243			`verilogSourceinclude`
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263			`CPU_ADD16`
264			`RAM_WORDS2048`
265			`RAM_ADD11`
266			`ROM_WORDS4096`
267			`ROM_ADD12`
268			`PROG_ROM_WORDS4096`
269			`PROG_ROM_ADD12`
270			`VEC_TABLE8'hff`
271			`UART_PRESCALE5'b01100`
272			`UART_PRE_SIZE5`
273			`UART_DIV0`
274			`JTAG_SEL1`
275
276
277
278
279
280
281
282
283			`Hierarchical`
284
285
286			`spirit:library="Mos6502"`
287			`spirit:name="T6502"`
288			`spirit:version="def.design"/>`
289
290
291
292
293			`verilog`
294
295
296			`spirit:library="Testbench"`
297			`spirit:name="toolflow"`
298			`spirit:version="verilog"/>`
299
300
301
302
303
304
305
306
307			`commoncommon`
308			`Verilog`
309
310
311
312
313			`sim:Simulation:`
314			`Verilog`
315
316			`fs-sim`
317
318
319
320			`syn:Synthesis:`
321			`Verilog`
322
323			`fs-sim`
324
325
326
327
328			`syn2:Synthesis:`
329			`Verilog`
330
331			`fs-syn`
332
333
334
335
336
337
338
339			`doc`
340
341
342			`spirit:library="Testbench"`
343			`spirit:name="toolflow"`
344			`spirit:version="documentation"/>`
345
346			`:Documentation:`
347			`Verilog`
348
349
350
351
352
353
354
355
356
357
358
359
360
361			`ext_addr`
362			`wire`
363			`out231`
364
365
366
367			`ext_wdata`
368			`wire`
369			`out150`
370
371
372
373			`ext_rdata`
374			`wire`
375			`in150`
376
377
378
379
380			`ext_ub`
381			`wire`
382			`out`
383
384
385			`ext_wait`
386			`wire`
387			`in`
388
389
390			`ext_lb`
391			`wire`
392			`out`
393
394
395			`ext_rd`
396			`wire`
397			`out`
398
399
400			`ext_stb`
401			`wire`
402			`out`
403
404
405			`ext_wr`
406			`wire`
407			`out`
408
409
410			`ext_cs`
411			`wire`
412			`out10`
413
414
415
416			`alu_status`
417			`wire`
418			`out70`
419
420
421			`cts_pad_in`
422			`wire`
423			`in`
424
425
426			`rts_pad_out`
427			`wire`
428			`out`
429
430
431
432			`gpio_0_out`
433			`wire`
434			`out70`
435
436
437			`gpio_0_oe`
438			`wire`
439			`out70`
440
441
442
443			`gpio_0_in`
444			`wire`
445			`in70`
446
447
448			`gpio_1_out`
449			`wire`
450			`out70`
451
452
453			`gpio_1_oe`
454			`wire`
455			`out70`
456
457
458
459			`gpio_1_in`
460			`wire`
461			`in70`
462
463
464			`ext_irq_in`
465			`wire`
466			`in30`
467
468
469
470
471
472			`jsp_data_out`
473			`wire`
474			`out70`
475
476
477
478
479			`wb_jsp_dat_i`
480			`wire`
481			`in70`
482
483
484
485			`biu_wr_strobe`
486			`wire`
487			`out`
488
489
490
491			`wb_jsp_stb_i`
492			`wire`
493			`in`
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520