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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 134

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xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
xmlns:socgen="http://opencores.org"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009
http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">
 
opencores.org
Mos6502
T6502
def  default
 

 
 slave_clk
  
  
  
    
      
        clk
        clk
      
    
 
 
 
 slave_reset
  
  
  
    
      
        reset
        reset
      
    
 
 
 
 
 
 
 
 
 jtag
  
  
    
 
      
        shiftcapture_dr_clk
        jtag_shiftcapture_dr_clk
      
 
 
      
        test_logic_reset
        jtag_test_logic_reset
      
 
      
        capture_dr
        jtag_capture_dr
      
 
      
        shift_dr
        jtag_shift_dr
      
 
      
        update_dr_clk
        jtag_update_dr_clk
      
 
 
      
        tdi
        jtag_tdi
      
 
      
        tdo
        jtag_tdo
      
 
      
        select
        jtag_select
      
 
    
 
 
 
 

 
 

 
 

  gen_verilog
  104.0
  none
  common
  ./tools/verilog/gen_verilog
    
    
      destination
      T6502_def
    
  

 
 
 
 
 
 
 
 
 

 
 
 
 

 
   
      fs-common
 
      
        
        ../verilog/top.rtl
        verilogSourcefragment
      
 
 
   
 
 
 
   
      fs-sim
 
      
        
        ../verilog/copyright.v
        verilogSourceinclude
      
 
      
        
        ../verilog/common/T6502_def
        verilogSourcemodule
      
 
 
 
   
 
   
      fs-syn
 
      
        
        ../verilog/syn.v
        verilogSourceinclude
      
 
 
 
   
 
 

 
 
 
 
 
 
 

 

    CPU_ADD16
    VEC_TABLE8'hff
    BOOT_ROM_WIDTH16
    ROM_WRITETHRU0

 
 
 
 
   
 
 
              
              Hierarchical
 
              
                                   spirit:library="Mos6502"
                                   spirit:name="T6502"
                                   spirit:version="def.design"/>
              
 
 
              
              verilog
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="verilog"/>
              
              
 
 
 
 
 
     
     commoncommon
     Verilog
     
     
 
     
     sim:*Simulation:*
      Verilog
     
     fs-sim
     
 
     
     syn:*Synthesis:*
      Verilog
     
     fs-sim
     
 
 
     
     syn2:*Synthesis:*
      Verilog
     
     fs-syn
     
 
 
 
 
 
              
              doc
              
              
                                   spirit:library="Testbench"
                                   spirit:name="toolflow"
                                   spirit:version="documentation"/>
              
              :*Documentation:*
              Verilog
              
 
 
 
 
   
 
 
 

 
 

ext_addr
wire
out231

 

ext_wdata
wire
out150

 

ext_rdata
wire
in150

 
 

ext_ub
wire
out

 
ext_wait
wire
in

 
ext_lb
wire
out

 
ext_rd
wire
out

 
ext_stb
wire
out

 
ext_wr
wire
out

 
ext_cs
wire
out10

 
 
alu_status
wire
out70

 
cts_pad_in
wire
in

 
rts_pad_out
wire
out

 
 
gpio_0_out
wire
out70

 
gpio_0_oe
wire
out70

 
 
gpio_0_in
wire
in70

 
gpio_1_out
wire
out70

 
gpio_1_oe
wire
out70

 
 
gpio_1_in
wire
in70

 
ext_irq_in
wire
in30

 
 
 
 
jsp_data_out
wire
out70

 
 
 
wb_jsp_dat_i
wire
in70

 
 
biu_wr_strobe
wire
out

 
 
wb_jsp_stb_i
wire
in

 
 
 
 
 

 

 
 
 
 
 
 
 
 
 
 
 

 
 
 
 
 
 

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Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [rtl/] [xml/] [T6502_def.xml] - Blame information for rev 134

Line No.	Rev	Author	Line
1	131	jt_eaton
2
30
31			`xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"`
32			`xmlns:socgen="http://opencores.org"`
33			`xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"`
34			`xsi:schemaLocation="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009`
35			`http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009/index.xsd">`
36
37			`opencores.org`
38			`Mos6502`
39			`T6502`
40			`def default`
41
42
43
44			`slave_clk`
45
46
47
48
49
50			`clk`
51			`clk`
52
53
54
55
56
57			`slave_reset`
58
59
60
61
62
63			`reset`
64			`reset`
65
66
67
68
69
70
71
72
73
74
75			`jtag`
76
77
78
79
80
81			`shiftcapture_dr_clk`
82			`jtag_shiftcapture_dr_clk`
83
84
85
86
87			`test_logic_reset`
88			`jtag_test_logic_reset`
89
90
91
92			`capture_dr`
93			`jtag_capture_dr`
94
95
96
97			`shift_dr`
98			`jtag_shift_dr`
99
100
101
102			`update_dr_clk`
103			`jtag_update_dr_clk`
104
105
106
107
108			`tdi`
109			`jtag_tdi`
110
111
112
113			`tdo`
114			`jtag_tdo`
115
116
117
118			`select`
119			`jtag_select`
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134			`gen_verilog`
135			`104.0`
136			`none`
137			`common`
138			`./tools/verilog/gen_verilog`
139
140
141			`destination`
142	134	jt_eaton	`T6502_def`
143	131	jt_eaton
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163			`fs-common`
164
165
166
167			`../verilog/top.rtl`
168			`verilogSourcefragment`
169
170
171
172
173
174
175
176
177			`fs-sim`
178
179
180
181			`../verilog/copyright.v`
182			`verilogSourceinclude`
183
184
185
186
187	134	jt_eaton	`../verilog/common/T6502_def`
188	131	jt_eaton	`verilogSourcemodule`
189
190
191
192
193
194
195
196			`fs-syn`
197
198
199
200			`../verilog/syn.v`
201			`verilogSourceinclude`
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220			`CPU_ADD16`
221			`VEC_TABLE8'hff`
222	133	jt_eaton	`BOOT_ROM_WIDTH16`
223			`ROM_WRITETHRU0`
224	131	jt_eaton
225
226
227	133	jt_eaton
228	131	jt_eaton
229
230
231
232
233			`Hierarchical`
234
235
236			`spirit:library="Mos6502"`
237			`spirit:name="T6502"`
238			`spirit:version="def.design"/>`
239
240
241
242
243			`verilog`
244
245
246			`spirit:library="Testbench"`
247			`spirit:name="toolflow"`
248			`spirit:version="verilog"/>`
249
250
251
252
253
254
255
256
257			`commoncommon`
258			`Verilog`
259
260
261
262
263			`sim:Simulation:`
264			`Verilog`
265
266			`fs-sim`
267
268
269
270			`syn:Synthesis:`
271			`Verilog`
272
273			`fs-sim`
274
275
276
277
278			`syn2:Synthesis:`
279			`Verilog`
280
281			`fs-syn`
282
283
284
285
286
287
288
289			`doc`
290
291
292			`spirit:library="Testbench"`
293			`spirit:name="toolflow"`
294			`spirit:version="documentation"/>`
295
296			`:Documentation:`
297			`Verilog`
298
299
300
301
302
303
304
305
306
307
308
309
310
311			`ext_addr`
312			`wire`
313			`out231`
314
315
316
317			`ext_wdata`
318			`wire`
319			`out150`
320
321
322
323			`ext_rdata`
324			`wire`
325			`in150`
326
327
328
329
330			`ext_ub`
331			`wire`
332			`out`
333
334
335			`ext_wait`
336			`wire`
337			`in`
338
339
340			`ext_lb`
341			`wire`
342			`out`
343
344
345			`ext_rd`
346			`wire`
347			`out`
348
349
350			`ext_stb`
351			`wire`
352			`out`
353
354
355			`ext_wr`
356			`wire`
357			`out`
358
359
360			`ext_cs`
361			`wire`
362			`out10`
363
364
365
366			`alu_status`
367			`wire`
368			`out70`
369
370
371			`cts_pad_in`
372			`wire`
373			`in`
374
375
376			`rts_pad_out`
377			`wire`
378			`out`
379
380
381
382			`gpio_0_out`
383			`wire`
384			`out70`
385
386
387			`gpio_0_oe`
388			`wire`
389			`out70`
390
391
392
393			`gpio_0_in`
394			`wire`
395			`in70`
396
397
398			`gpio_1_out`
399			`wire`
400			`out70`
401
402
403			`gpio_1_oe`
404			`wire`
405			`out70`
406
407
408
409			`gpio_1_in`
410			`wire`
411			`in70`
412
413
414			`ext_irq_in`
415			`wire`
416			`in30`
417
418
419
420
421
422			`jsp_data_out`
423			`wire`
424			`out70`
425
426
427
428
429			`wb_jsp_dat_i`
430			`wire`
431			`in70`
432
433
434
435			`biu_wr_strobe`
436			`wire`
437			`out`
438
439
440
441			`wb_jsp_stb_i`
442			`wire`
443			`in`
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470