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[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [Mos6502/] [ip/] [T6502/] [sim/] [testbenches/] [verilog/] [tb.ext_m] - Blame information for rev 131

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Line No. Rev Author Line
1 131 jt_eaton
assign ext_irq_in = 4'h0;
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pullup mdb_00(MEMDB[00]);
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pullup mdb_01(MEMDB[01]);
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pullup mdb_02(MEMDB[02]);
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pullup mdb_03(MEMDB[03]);
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pullup mdb_04(MEMDB[04]);
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pullup mdb_05(MEMDB[05]);
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pullup mdb_06(MEMDB[06]);
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pullup mdb_07(MEMDB[07]);
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pullup mdb_08(MEMDB[08]);
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pullup mdb_09(MEMDB[09]);
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pullup mdb_10(MEMDB[10]);
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pullup mdb_11(MEMDB[11]);
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pullup mdb_12(MEMDB[12]);
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pullup mdb_13(MEMDB[13]);
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pullup mdb_14(MEMDB[14]);
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pullup mdb_15(MEMDB[15]);
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pullup pu_ramwait ( ramwait_in );
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mt45w8mw12_def
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psram (
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    .clk    ( ramclk_out    ),
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    .adv_n  ( ramadv_n_out  ),
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    .cre    ( ramcre_out    ),
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    .o_wait ( ramwait_in    ),
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    .ce_n   ( ramcs_n_out   ),
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    .oe_n   ( memoe_n_out   ),
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    .we_n   ( memwr_n_out   ),
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    .lb_n   ( ramlb_n_out   ),
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    .ub_n   ( ramub_n_out   ),
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    .addr   ( memadr_out    ),
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    .dq     ( MEMDB         )
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);
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assign STOP = 1'b0;
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assign BAD = 1'b0;

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